公开(公告)号：US5915203A

公开(公告)日：1999-06-22

申请号：US872562

申请日：1997-06-10

Applicant: Samit Sengupta ,  Subhas Bothra

Inventor： Samit Sengupta ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/5226 ,  H01L21/76819 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

Abstract translation: 描述了生产深亚微米通孔的方法，其中金属覆盖层形成在金属前电介质上并被图案化以形成线元件。 然后将金属间电介质沉积在图案化的金属上，并化学机械地抛光到线元件的顶部。 然后沉积和图案化第二金属覆盖层以形成通孔螺柱。 金属间电介质也通过螺柱沉积在图案化的金属上，并被抛光到螺柱的顶部。 重复该过程，直到形成多层集成电路。

公开(公告)号：US5882997A

公开(公告)日：1999-03-16

申请号：US955030

申请日：1997-10-21

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC: G11C11/412 ,  H01L21/02 ,  H01L27/11 ,  H01L21/44

CPC classification number: H01L28/20 ,  G11C11/412 ,  H01L27/1112

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract translation: 用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。 电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。 有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

公开(公告)号：US5877562A

公开(公告)日：1999-03-02

申请号：US925040

申请日：1997-09-08

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: G03F9/00 ,  H01L23/544 ,  H01L23/58

CPC classification number: G03F9/708 ,  G03F9/70 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract translation: 与基板一体的光取向结构使得对准装置能够接收对准结构的表面形貌的反射光标记。 当构建电路时，可以与该过程一起构建对准目标。 对准结构被构造成使得其表面将保持足够的形貌以使对准装置能够正确对准。

公开(公告)号：US5783488A

公开(公告)日：1998-07-21

申请号：US594874

申请日：1996-01-31

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC classification number: H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/522 ,  H01L2924/0002

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

公开(公告)号：US08274353B2

公开(公告)日：2012-09-25

申请号：US13047699

申请日：2011-03-14

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US20090127654A1

公开(公告)日：2009-05-21

申请号：US12360068

申请日：2009-01-26

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01L27/02

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US06545338B1

公开(公告)日：2003-04-08

申请号：US09429586

申请日：1999-10-28

Applicant: Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff ,  Milind Weling

Inventor： Subhas Bothra ,  Calvin Todd Gabriel ,  Michael Misheloff ,  Milind Weling

IPC: H01L2900

CPC classification number: H01L23/5225 ,  H01L21/76885 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/00

Abstract: A method for making a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer, and a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer is provided. The method includes forming a lower metallization layer and a lower dielectric layer over the lower metallization layer. A metallization line is formed over the lower dielectric layer with an upper dielectric layer over the metallization line. An upper metallization layer is then formed over the upper dielectric layer. After this is completed, oxide spacers are formed along the sides of the lower dielectric layer, the metallization line, and the upper dielectric layer. Finally, an encapsulating metallization layer is formed over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield and the metallization line defines an inner conductor of an RF line.

Abstract translation: 提供了一种用于制造具有在半导体晶片上制造的集成CMOS电路和RF电路的半导体器件的方法，以及在半导体晶片上制造的具有集成CMOS电路和RF电路的半导体器件。 该方法包括在下金属化层上形成下金属化层和下电介质层。 金属化线形成在下电介质层上方，在金属化线上方具有上介电层。 然后在上电介质层上形成上金属化层。 完成之后，沿下电介质层，金属化线和上电介质层的侧面形成氧化物间隔物。 最后，在氧化物间隔物之上形成封装的金属化层，使得下金属化层，上金属化层和封装金属化层限定外屏蔽，并且金属化线限定RF线的内导体。

公开(公告)号：US06387797B1

公开(公告)日：2002-05-14

申请号：US09234292

申请日：1999-01-20

Applicant: Subhas Bothra ,  Rao Annapragada

Inventor： Subhas Bothra ,  Rao Annapragada

IPC: H01L214763

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Abstract translation: 提供一种制造半导体的方法，其避免了在互连之间的电介质中形成的空隙中的金属沉积。 在优选实施例中，蚀刻停止凹部部分设置在电介质上，封装互连件以防止在蚀刻通孔孔期间通孔开口延伸到空隙中。 因此，避免了在通孔的金属沉积期间空隙的金属沉积。 结果，如此形成的半导体具有减小互连之间的电容并提高可靠性，因为空隙被任何金属沉积清除。

公开(公告)号：US06277708B1

公开(公告)日：2001-08-21

申请号：US09396104

申请日：1999-09-14

Applicant: Subhas Bothra ,  Harlan Lee Sur, Jr.

Inventor： Subhas Bothra ,  Harlan Lee Sur, Jr.

IPC: H01L2176

CPC classification number: H01L21/28525 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0814 ,  H01L29/861

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract translation: 公开了半导体二极管结构以及用于制造用于抑制晶体管栅极氧化物等离子体充电损坏的半导体二极管结构的方法。 半导体二极管结构包括被配置为隔离半导体衬底的有源区的浅沟槽隔离区。 一种具有第一端和第二端的掺杂多晶硅电极。 掺杂多晶硅电极限定在浅沟槽隔离区域中，并且第一端被配置为与半导体衬底电接触。 二极管结构还包括具有底层栅极氧化物的多晶硅栅极。 多晶硅栅极被限定在有源区上并且在浅沟槽隔离区的一部分上延伸，以便在多晶硅栅极和掺杂多晶硅电极的第二端之间形成电互连。

公开(公告)号：US06275971B1

公开(公告)日：2001-08-14

申请号：US08941898

申请日：1997-09-30

Applicant: Harold J. Levy ,  Subhas Bothra ,  David C. Chapman

Inventor： Harold J. Levy ,  Subhas Bothra ,  David C. Chapman

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.

Abstract translation: 公开了一种用于检查集成电路布局设计文件的方法。 该方法包括识别布局在通孔掩模文件上的通孔几何。 识别在金属化掩模文件上布置的金属化几何。 在第一方向移动通孔几何以产生第一移位通孔几何形状。 在第一移位通孔几何和金属化几何之间执行逻辑AND。 该方法还包括确定逻辑“否”是否产生指示所识别的金属化几何形状和第一偏移通道几何之间的足够重叠的值。