公开(公告)号：US06176983B1

公开(公告)日：2001-01-23

申请号：US08923384

申请日：1997-09-03

Applicant: Subhas Bothra ,  Dipankar Pramanik ,  Samit Sengupta

Inventor： Subhas Bothra ,  Dipankar Pramanik ,  Samit Sengupta

IPC: C23C1434

CPC classification number: C23C14/046 ,  C23C14/345 ,  C23C14/35 ,  H01L21/76843 ,  H01L21/76877

Abstract: The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural sidewalls joining a bottom surface at respective plural corners; first sputtering a process layer upon at least a portion of the bottom surface using ionized metal plasma physical vapor deposition; and following the sputtering of the process layer, second sputtering at least some of the process layer towards the corners within the via.

Abstract translation: 本发明提供了形成半导体工件的方法。 根据本发明的形成半导体器件的一种方法包括：提供半导体工件; 在所述半导体工件内形成通孔，所述通孔包括在相应的多个拐角处连接底表面的多个侧壁; 首先使用电离金属等离子体物理气相沉积在底表面的至少一部分上溅射处理层; 并且在溅射工艺层之后，将工艺层中的至少一些朝向通孔内的拐角第二溅射。

公开(公告)号：US5915203A

公开(公告)日：1999-06-22

申请号：US872562

申请日：1997-06-10

Applicant: Samit Sengupta ,  Subhas Bothra

Inventor： Samit Sengupta ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/5226 ,  H01L21/76819 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

Abstract translation: 描述了生产深亚微米通孔的方法，其中金属覆盖层形成在金属前电介质上并被图案化以形成线元件。 然后将金属间电介质沉积在图案化的金属上，并化学机械地抛光到线元件的顶部。 然后沉积和图案化第二金属覆盖层以形成通孔螺柱。 金属间电介质也通过螺柱沉积在图案化的金属上，并被抛光到螺柱的顶部。 重复该过程，直到形成多层集成电路。

公开(公告)号：US07286020B1

公开(公告)日：2007-10-23

申请号：US11231641

申请日：2005-09-21

Applicant: Hugh Sungki O ,  Samit Sengupta ,  Joseph Michael Ingino, Jr.

Inventor： Hugh Sungki O ,  Samit Sengupta ,  Joseph Michael Ingino, Jr.

IPC: G01R31/00 ,  G01R23/00 ,  H03K19/003 ,  G06F11/16

CPC classification number: H03K19/00315 ,  H03K19/00369

Abstract: Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first periodic signal to the frequency of a second periodic signal. The difference in the frequency between the first periodic signal and the second periodic signal indirectly indicates how much the threshold voltages of the transistors have shifted. The difference in frequency between the two periodic signals can be monitored to determine the speed and performance of circuits on the chip. The output of the frequency detector can also indicate when to replace low performing circuits with higher performing circuits. When the frequency of the second periodic signal differs from the frequency of the first periodic signal by a predefined percentage, a low performing circuit is replaced with a higher performing replica circuit.

Abstract translation: 提供技术用于监视电路的性能，并用更高性能的电路代替低性能电路。 频率检测器将第一周期信号的频率与第二周期信号的频率进行比较。 第一周期信号和第二周期信号之间的频率差异间接地指示晶体管的阈值电压已经偏移了多少。 可以监视两个周期信号之间的频率差，以确定芯片上电路的速度和性能。 频率检测器的输出也可以指示什么时候更换具有较高性能电路的低性能电路。 当第二周期信号的频率与预定百分比的第一周期信号的频率不同时，低执行电路被更高性能的复制电路代替。

公开(公告)号：US06433433B1

公开(公告)日：2002-08-13

申请号：US09593322

申请日：2000-06-13

Applicant: Samit Sengupta

Inventor： Samit Sengupta

IPC: H01L2348

CPC classification number: H01L21/7685 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886

Abstract: A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF6 during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.

Abstract translation: 半导体器件包括半导体衬底，例如其上布置有氧化层的硅晶片的一部分。 金属堆叠设置在半导体衬底之上，并且电介质层设置在金属叠层上。 电介质层具有形成在其中的通孔，其与金属堆叠不对准，使得通孔的一部分延伸超过金属堆叠的顶部并且暴露金属叠层的一个侧壁的至少一部分。 侧壁盖层形成在金属叠层的侧壁的暴露部分上。 侧壁盖层构造成在钨的化学气相沉积期间抵抗WF6的显着穿透。 侧壁盖层可以是氮化层或电介质材料层。 由钨组成的导电材料设置在通孔中并基本上填充通孔。 还描述了在半导体器件中制造导电通孔的方法。

公开(公告)号：US06410421B1

公开(公告)日：2002-06-25

申请号：US09560939

申请日：2000-04-28

Applicant: Kouros Ghandehari ,  Samit Sengupta

Inventor： Kouros Ghandehari ,  Samit Sengupta

IPC: H01L214763

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/32139

Abstract: A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful for patterning the metal layers with light having a wavelength of 190-300 nm. The anti-reflective structure may be a single indium tin oxide layer or may include a titanium nitride layer formed over the metal layer and an indium tin oxide layer formed over the titanium nitride layer. For many applications, the anti-reflective structure, in the presence of a photoresist layer, has a reflectivity of about 3% or less for light having a wavelength of 190-300 nm.

Abstract translation: 半导体器件包括用于在半导体器件中图案化金属层的抗反射结构。 抗反射结构至少部分地使用氧化铟锡制成。 抗反射结构对于波长为190-300nm的光图案化金属层是特别有用的。 抗反射结构可以是单个氧化铟锡层，或者可以包括在金属层上形成的氮化钛层和形成在氮化钛层上的氧化铟锡层。 对于许多应用，在光致抗蚀剂层存在的情况下，抗反射结构对波长为190-300nm的光具有约3％以下的反射率。

公开(公告)号：US6146996A

公开(公告)日：2000-11-14

申请号：US145017

申请日：1998-09-01

Applicant: Samit Sengupta

Inventor： Samit Sengupta

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/7685 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886

Abstract: A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF.sub.6 during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.

Abstract translation: 半导体器件包括半导体衬底，例如其上布置有氧化层的硅晶片的一部分。 金属堆叠设置在半导体衬底之上，并且电介质层设置在金属叠层上。 电介质层具有形成在其中的通孔，其与金属堆叠不对准，使得通孔的一部分延伸超过金属堆叠的顶部并且暴露金属叠层的一个侧壁的至少一部分。 侧壁盖层形成在金属叠层的侧壁的暴露部分上。 侧壁盖层构造成在钨的化学气相沉积期间抵抗WF6的显着穿透。 侧壁盖层可以是氮化层或电介质材料层。 由钨组成的导电材料设置在通孔中并基本上填充通孔。 还描述了在半导体器件中制造导电通孔的方法。

公开(公告)号：US6057587A

公开(公告)日：2000-05-02

申请号：US919911

申请日：1997-08-28

Applicant: Kouros Ghandehari ,  Samit Sengupta

Inventor： Kouros Ghandehari ,  Samit Sengupta

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L31/0232 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/32139

Abstract: A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful for patterning the metal layers with light having a wavelength of 190-300 nm. The anti-reflective structure may be a single indium tin oxide layer or may include a titanium nitride layer formed over the metal layer and an indium tin oxide layer formed over the titanium nitride layer. For many applications, the anti-reflective structure, in the presence of a photoresist layer, has a reflectivity of about 3% or less for light having a wavelength of 190-300 nm.

Abstract translation: 半导体器件包括用于在半导体器件中图案化金属层的抗反射结构。 抗反射结构至少部分地使用氧化铟锡制成。 抗反射结构对于波长为190-300nm的光图案化金属层是特别有用的。 抗反射结构可以是单个氧化铟锡层，或者可以包括在金属层上形成的氮化钛层和形成在氮化钛层上的氧化铟锡层。 对于许多应用，在光致抗蚀剂层存在的情况下，抗反射结构对波长为190-300nm的光具有约3％以下的反射率。

公开(公告)号：US07468617B1

公开(公告)日：2008-12-23

申请号：US11605516

申请日：2006-11-28

Applicant: Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

Inventor： Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

IPC: H03K19/094 ,  H02H9/00

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

Abstract translation: 一方面，本发明包括一种静电放电（ESD）保护电路，其包括多个输入电路，其中每个输入电路包括串联连接在电源与地之间的第一PMOS和第一NMOS晶体管以及第一和第二反相器 连接到第一PMOS和NMOS晶体管的栅极。 连接到第一NMOS晶体管的栅极的每个反相器包括连接在该栅极和地之间的第二NMOS晶体管，并且第二NMOS晶体管的栅极宽度与第一NMOS晶体管的栅极宽度之比 输入电路基本相同。 在本发明的另一方面，多指栅极晶体管形成在一个导电类型的第一阱中，该第一阱由相同导电类型的第二阱围绕，该第二阱由浅沟槽隔离和一部分 基质。 第二个阱用作第一个阱的抽头，而衬底电流路径的电阻显着增加。 形成该结构的方法是本发明的另一方面。

公开(公告)号：US06933869B1

公开(公告)日：2005-08-23

申请号：US10802590

申请日：2004-03-17

Applicant: Greg Starr ,  Samit Sengupta ,  Hugh SungKi O

Inventor： Greg Starr ,  Samit Sengupta ,  Hugh SungKi O

IPC: G11C5/14 ,  H03M1/10

CPC classification number: G11C29/028 ,  G11C5/147 ,  G11C29/12005 ,  G11C2029/5002

Abstract: Integrated circuits are stabilized by monitoring changes that affect circuit operation and by compensating for those changes using power supply adjustments. Changes in operating temperature and threshold voltage changes may be measured. Differential measurements may be made in which threshold voltages measured in continuously-biased monitoring circuits are compared to threshold voltages measured in intermittently-biased monitoring circuits. Temperature changes may be monitored using a temperature monitoring circuit based on an adjustable current source and a diode. Monitoring and compensation circuitry on the integrated circuits may use analog-to-digital and digital-to-analog converters controlled by a control unit to make temperature and threshold voltage measurements and corresponding compensating changes in power supply voltages.

Abstract translation: 通过监控影响电路运行的变化并通过使用电源调整来补偿这些变化来使集成电路稳定。 可以测量工作温度和阈值电压变化的变化。 可以进行差分测量，其中在连续偏置的监测电路中测量的阈值电压与在间歇偏置的监测电路中测量的阈值电压进行比较。 可以使用基于可调电流源和二极管的温度监测电路监测温度变化。 集成电路上的监控和补偿电路可以使用由控制单元控制的模数转换器和数模转换器来进行温度和阈值电压测量以及相应的电源电压补偿变化。

公开(公告)号：US06207565B1

公开(公告)日：2001-03-27

申请号：US09483461

申请日：2000-01-13

Applicant: Edward K. Yeh ,  Calvin Todd Gabriel ,  Samit Sengupta

Inventor： Edward K. Yeh ,  Calvin Todd Gabriel ,  Samit Sengupta

IPC: C09K1300

CPC classification number: H01L21/31138 ,  G03F7/427

Abstract: A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H2O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O2 plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.

Abstract translation: 一种制备用于随后的硅化物形成的半导体衬底的方法。 在一个实施例中，本发明使半导体衬底处于灰化环境。 在本实施例中，灰化环境由H 2 O蒸气和气态碳氟化合物或氟化烃气体构成。 这样做时，去除了半导体衬底上的杂质。 接下来，本发明将覆盖多晶硅堆叠的掩模用于掩模去除灰化环境。 在本实施例中，掩模去除灰化环境由O 2等离子体构成。 这样做，去除覆盖多晶硅叠层的掩模。 结果，半导体衬底和多晶硅堆叠的顶表面被准备用于随后在其上形成硅化物。