公开(公告)号：US06132521A

公开(公告)日：2000-10-17

申请号：US467132

申请日：1999-12-20

申请人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

发明人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

IPC分类号： C11D3/20 ,  C11D3/39 ,  C23G5/032 ,  B08B3/04

CPC分类号： C11D3/2072 ,  C11D3/2003 ,  C11D3/2093 ,  C11D3/3945 ,  C23G5/032 ,  Y10S134/902

摘要： A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution includes an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.

摘要翻译： 描述了从设备硬件表面清除元素铜，钴或镍的方法，而不会在晶片断裂和非晶片断裂的情况下腐蚀或损坏设备部件和表面。 溶液包括烷基二酮过氧化物，稳定剂，醇用于氧化金属并形成由清洗溶液除去的可溶性络合物。 此外，提供了在晶片断裂和非晶片断裂的情况下从设备硬件的表面清除元素铜，钴或镍的烷基二氧化碳过氧化物溶液。

公开(公告)号：US06394114B1

公开(公告)日：2002-05-28

申请号：US09442312

申请日：1999-11-22

申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

IPC分类号： C23G114

CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

摘要翻译： 描述了在制造集成电路中的便宜且安全的铜去除方法。 通过包含铵盐，胺和水的化学混合物将铜剥离或除去。 可以通过改变铵盐组分的浓度和混合物中的水量来控制铜汽提速率。 还提供了一种用于剥离铜并除去铜污染物的新型化学混合物。 用于除去或剥离铜的新型化学混合物包括铵盐，胺和水。 例如，新型化学混合物可以包含比例为1:1:1的氟化铵，水和乙二胺。

公开(公告)号：US06165891A

公开(公告)日：2000-12-26

申请号：US435434

申请日：1999-11-22

申请人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

IPC分类号： H01L21/311 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  G03C5/00 ,  H01L21/302 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/31122 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.

摘要翻译： 通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。 该方法开始于提供其上具有第一导电层的半导体结构。 在第一导电层上形成钝化层。 第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。 第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。 图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。 碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。 可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。 硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。

公开(公告)号：US06436824B1

公开(公告)日：2002-08-20

申请号：US09346526

申请日：1999-07-02

申请人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

发明人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

IPC分类号： H01L2144

CPC分类号： H01L21/02211 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/3125 ,  H01L21/314 ,  H01L21/76807

摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

摘要翻译： 提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。 通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。 此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。 通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。 或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。 此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。

公开(公告)号：US06352921B1

公开(公告)日：2002-03-05

申请号：US09619377

申请日：2000-07-19

申请人： Licheng M. Han ,  Yi Xu ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

发明人： Licheng M. Han ,  Yi Xu ,  Joseph Zhifeng Xie ,  Mei Sheng Zhou ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

公开(公告)号：US06331479B1

公开(公告)日：2001-12-18

申请号：US09398294

申请日：1999-09-20

申请人： Jianxun Li ,  Mei Sheng Zhou ,  Yi Xu ,  Simon Chooi

发明人： Jianxun Li ,  Mei Sheng Zhou ,  Yi Xu ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76835

摘要： A method of fabricating trenches has been achieved. The method may be applied to damascene and dual damascene contacts to prevent damage to organic low dielectric constant materials due to photoresist ashing. A semiconductor substrate is provided. A first dielectric layer is deposited overlying the semiconductor substrate. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. An optional anti-reflective coating is applied. A photoresist layer is deposited. The photoresist layer is patterned to define openings for planned trenches. The second etch stopping layer is etched through to form a hard mask for the planned trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals. The first etch stopping layer is etched through to complete the trenches, and the integrated circuit device is completed.

摘要翻译： 已经实现了制造沟槽的方法。 该方法可以应用于镶嵌和双镶嵌接触，以防止由于光致抗蚀剂灰化而损坏有机低介电常数材料。 提供半导体衬底。 沉积在半导体衬底上的第一介电层。 第一蚀刻停止层沉积在第一介电层上。 第二蚀刻停止层沉积在第一蚀刻停止层上。 应用可选的抗反射涂层。 沉积光致抗蚀剂层。 图案化光致抗蚀剂层以限定计划沟槽的开口。 蚀刻第二蚀刻停止层以形成用于所计划的沟槽的硬掩模。 光致抗蚀剂层通过灰化被剥离，其中第一蚀刻停止层保护第一介电层免受由于氧自由基的存在的损害。 蚀刻第一蚀刻停止层以完成沟槽，并且完成集成电路器件。

公开(公告)号：US06690091B1

公开(公告)日：2004-02-10

申请号：US09666316

申请日：2000-09-21

申请人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

IPC分类号： H01L2348

CPC分类号： H01L21/76835 ,  H01L21/31122 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and the cap layers comprise low dielectric constant materials carbon nitride, boron nitride, or boron carbon nitride. The stack is patterned to form a via opening to the first conductive layer. A trench opening is formed stopping on the etch stop layer. A barrier layer of TaN, WN, TaSiN or Ta and a second conductive material is applied to the openings. Passivation, etch stop, or cap layers can be formed with carbon nitride by magnetron sputtering from a graphite target in a nitrogen atmosphere; boron carbon nitride by magnetron sputtering from a graphite target in a nitrogen and B2H6 atmosphere; or boron nitride by PECVD using B2H6, ammonia, and nitrogen.

摘要翻译： 具有减小的电容电介质堆叠的镶嵌结构包括在半导体上形成的第一导电层上的钝化，第一电介质，蚀刻停止层，第二介电层和覆盖层。 钝化，蚀刻停止和盖层包括低介电常数材料碳氮化物，氮化硼或氮碳化硼。 图案化堆叠以形成到第一导电层的通孔。 形成停止在蚀刻停止层上的沟槽开口。 将TaN，WN，TaSiN或Ta和第二导电材料的阻挡层施加到开口。 钝化，蚀刻停止或盖层可以通过在氮气气氛中的石墨靶磁控溅射由碳氮化物形成; 硼氮化物通过磁控溅射从石墨靶在氮气和B2H6气氛中; 或使用B2H6，氨和氮的PECVD的氮化硼。

公开(公告)号：US06524910B1

公开(公告)日：2003-02-25

申请号：US09670329

申请日：2000-09-27

申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

公开(公告)号：US06479383B1

公开(公告)日：2002-11-12

申请号：US10068823

申请日：2002-02-05

申请人： Simon Chooi ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Mei Sheng Zhou

IPC分类号： H01L2144

CPC分类号： H01L21/32134 ,  H01L21/28518 ,  H01L21/321

摘要： A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing product. The reactant gas preferably contains sulfur and oxygen. The reactant gas more preferably comprises sulfur dioxide or sulfur trioxide. The reactant gas is preferably heated and optionally exposed to a plasma. Next, the metal containing product is removed using a liquid, thereby removing at least portion of the metal layer from over the substrate.

摘要翻译： 一种在制造集成电路器件中从衬底上去除金属的方法。 本发明包括在衬底上提供金属层。 金属层暴露于反应气体中以形成至少含固体金属的产品。 反应气体优选含有硫和氧。 反应气体更优选包含二氧化硫或三氧化硫。 反应气体优选被加热并任选地暴露于等离子体。 接下来，使用液体除去含金属的产品，从而从基板上除去金属层的至少一部分。

公开(公告)号：US06429129B1

公开(公告)日：2002-08-06

申请号：US09594415

申请日：2000-06-16

申请人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

发明人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.