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115 条记录 (耗时 0.022 秒)

    Method for stripping copper in damascene interconnects
    3.
    发明授权
    Method for stripping copper in damascene interconnects 有权

    公开(公告)号：US06565664B2

    公开(公告)日：2003-05-20

    申请号：US10131519

    申请日：2002-04-24

    申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

    发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

    IPC分类号： C23G114

    CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

    摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

    Method of forming dual thickness gate dielectric structures via use of silicon nitride layers
    4.
    发明授权
    Method of forming dual thickness gate dielectric structures via use of silicon nitride layers 失效
    通过使用氮化硅层形成双厚度栅极电介质结构的方法

    公开(公告)号：US06524910B1

    公开(公告)日：2003-02-25

    申请号：US09670329

    申请日：2000-09-27

    申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

    发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

    IPC分类号： H01L21336

    CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

    摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

    摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

    Method for selective removal of unreacted metal after silicidation
    5.
    发明授权
    Method for selective removal of unreacted metal after silicidation 有权
    硅化后选择性去除未反应金属的方法

    公开(公告)号：US06479383B1

    公开(公告)日：2002-11-12

    申请号：US10068823

    申请日：2002-02-05

    申请人： Simon Chooi ,  Mei Sheng Zhou

    发明人： Simon Chooi ,  Mei Sheng Zhou

    IPC分类号： H01L2144

    CPC分类号： H01L21/32134 ,  H01L21/28518 ,  H01L21/321

    摘要： A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing product. The reactant gas preferably contains sulfur and oxygen. The reactant gas more preferably comprises sulfur dioxide or sulfur trioxide. The reactant gas is preferably heated and optionally exposed to a plasma. Next, the metal containing product is removed using a liquid, thereby removing at least portion of the metal layer from over the substrate.

    摘要翻译： 一种在制造集成电路器件中从衬底上去除金属的方法。 本发明包括在衬底上提供金属层。 金属层暴露于反应气体中以形成至少含固体金属的产品。 反应气体优选含有硫和氧。 反应气体更优选包含二氧化硫或三氧化硫。 反应气体优选被加热并任选地暴露于等离子体。 接下来，使用液体除去含金属的产品，从而从基板上除去金属层的至少一部分。

    Method for forming an extended metal gate using a damascene process
    8.
    发明授权
    Method for forming an extended metal gate using a damascene process 有权
    使用镶嵌工艺形成延伸金属浇口的方法

    公开(公告)号：US06303447B1

    公开(公告)日：2001-10-16

    申请号：US09502036

    申请日：2000-02-11

    申请人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

    发明人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

    IPC分类号： H01L21336

    CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

    摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

    摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中所述沟槽的宽度大于所述栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

    Method to deposit a copper layer
    9.
    发明授权
    Method to deposit a copper layer 失效
    沉积铜层的方法

    公开(公告)号：US06261954B1

    公开(公告)日：2001-07-17

    申请号：US09501968

    申请日：2000-02-10

    申请人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

    发明人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  C23C18/1608 ,  C25D7/123 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877

    摘要： A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer. The copper layer may comprise a thin seed layer for use in subsequent electroplating or electroless plating of copper or may comprise a thick copper layer to fill the vias and trenches. The integrated circuit is completed.

    摘要翻译： 已经实现了在制造集成电路器件中使用Cu（I）离子从由极性有机溶剂稳定的溶液中进行歧化的单层和双镶嵌互连的沉积铜层的新方法。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化电介质层以形成用于计划的双镶嵌互连的通孔和沟槽。 沉积覆盖在介电层上的阻挡层以对通孔和沟槽进行排列。 将由极性有机溶剂稳定的简单的Cu（I）离子溶液涂覆在所述阻挡层上。 向稳定化的简单的Cu（I）离子溶液中加入水以引起Cu（I）离子溶液中简单的Cu（I）离子的歧化。 沉积在屏障层上的铜层。 铜层可以包括用于铜的后续电镀或无电镀的薄种子层，或者可以包括用于填充通孔和沟槽的厚铜层。 集成电路完成。

    Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
    10.
    发明授权
    Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer 有权
    使用碳氮化物，氮化硼或氮化硼钝化层，蚀刻停止层和/或覆盖层的具有降低的电容的镶嵌结构

    公开(公告)号：US06165891A

    公开(公告)日：2000-12-26

    申请号：US435434

    申请日：1999-11-22

    申请人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

    发明人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

    IPC分类号： H01L21/311 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  G03C5/00 ,  H01L21/302 ,  H01L23/48

    CPC分类号： H01L21/76835 ,  H01L21/31122 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.

    摘要翻译： 通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。 该方法开始于提供其上具有第一导电层的半导体结构。 在第一导电层上形成钝化层。 第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。 第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。 图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。 碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。 可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。 硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。