公开(公告)号：US20120120577A1

公开(公告)日：2012-05-17

申请号：US12946328

申请日：2010-11-15

申请人： Sungjun Chun ,  Daniel M. Dreps ,  Dierk Kaller ,  Rohan U. Mandrekar ,  Lei Shan

发明人： Sungjun Chun ,  Daniel M. Dreps ,  Dierk Kaller ,  Rohan U. Mandrekar ,  Lei Shan

IPC分类号： G06F1/16

CPC分类号： G06F1/185 ,  G06F1/10

摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.

摘要翻译： 配置为连接到数据处理系统的时隙的存储器模块。 一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。 该组标签包括第一标签，第二标签，第三标签和第四标签。 第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。 第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。 第一和第三选项卡被配置为提供到时钟的第一电连接。 第二和第四选项卡被配置为提供与时钟的第二电连接。 一起，第一，第二，第三和第四标签包括两个双标签。

公开(公告)号：US07945881B2

公开(公告)日：2011-05-17

申请号：US11961440

申请日：2007-12-20

申请人： Sungjun Chun ,  Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen

发明人： Sungjun Chun ,  Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5077

摘要： A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window.

摘要翻译： 在物理电路布线设计中减少串扰引起的噪声的方法在物理电路布线设计中为每个互连线段构造空间矢量。 该方法比较了所述物理电路布线设计的空间矢量，并且识别彼此平行且具有相反方向的任何空间矢量。 该方法可以识别物理电路布线设计中的所有驱动器和接收器，并且从其驱动器开始追踪每个互连线，以确定从驱动器到互连线的每个段断点的路由长度。 该方法可以通过在物理电路布线设计中定义原点来构造空间矢量。 该方法确定相对于原点的空间矢量的起始点和终点。 空间矢量的起始点是互连线段靠近驾驶员的断点。 空间矢量的终点是互连线段远离驾驶员的断点。 该方法可以相对于原点定义笛卡尔坐标系。 笛卡尔坐标系可以与物理电路布线设计的互连线段正交。 该方法可以在物理电路布线设计中定义一个或多个几何窗口并比较每个几何窗口中的空间矢量。

公开(公告)号：US20110083888A1

公开(公告)日：2011-04-14

申请号：US12577259

申请日：2009-10-12

申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

IPC分类号： H05K1/02 ,  H05K3/10 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.

摘要翻译： 一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线 第一条信号线。 多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

公开(公告)号：US20100035426A1

公开(公告)日：2010-02-11

申请号：US12579517

申请日：2009-10-15

申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC分类号： H01L21/768 ,  G06F17/50

CPC分类号： H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

摘要： An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

摘要翻译： 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US07646082B2

公开(公告)日：2010-01-12

申请号：US11751786

申请日：2007-05-22

申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC分类号： H01L29/40 ,  H01L29/73 ,  H01L23/52

CPC分类号： H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

摘要： A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

摘要翻译： 具有改进的传输线完整性和增加的布线密度的多层电路基板和方法使用选择性地施加的传输线参考平面金属层来实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输之间的电容引起的阻抗下降 线参考平面金属层。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US20060214190A1

公开(公告)日：2006-09-28

申请号：US11086719

申请日：2005-03-22

申请人： Sungjun Chun ,  Jason Frankel ,  Anand Haridass ,  Erich Klink ,  Brian Singletary

发明人： Sungjun Chun ,  Jason Frankel ,  Anand Haridass ,  Erich Klink ,  Brian Singletary

IPC分类号： H01L27/10

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0306 ,  H05K3/4629 ,  H05K2201/09681 ,  H01L2924/00

摘要： A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.

摘要翻译： 提供了一种用于降低多层陶瓷封装中的噪声的系统和方法。 利用系统和方法，在没有信号通孔的地方，附加的屏蔽线插入参考平面。 参考平面中的这些附加线强制与参考（vdd / gnd）的信号相互作用更强，从而减少信号层中信号之间的相互作用。 结果，信号层的信号中存在的噪声降低。