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    Reducing crosstalk in the design of module nets
    4.
    发明授权
    Reducing crosstalk in the design of module nets 有权
    减少模块网设计中的串扰

    公开(公告)号：US08407644B2

    公开(公告)日：2013-03-26

    申请号：US12537767

    申请日：2009-08-07

    申请人： Dulce M. Altabella Cabrera ,  Sungjun Chun ,  Anand Haridass ,  Tingdong Zhou

    发明人： Dulce M. Altabella Cabrera ,  Sungjun Chun ,  Anand Haridass ,  Tingdong Zhou

    IPC分类号： G06F17/50

    CPC分类号： H01L23/5386 ,  G06F17/5077 ,  G06F2217/82 ,  H01L23/5222 ,  H01L23/552 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192

    摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.

    摘要翻译： 一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。 在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。 特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。 此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT
    5.
    发明申请
    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
    具有条带划分的参考平面电路的电路制造和设计技术

    公开(公告)号：US20120331429A1

    公开(公告)日：2012-12-27

    申请号：US13603732

    申请日：2012-09-05

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    Detecting open ground connections in surface mount connectors
    6.
    发明授权
    Detecting open ground connections in surface mount connectors 失效
    检测表面贴装连接器中的开放接地连接

    公开(公告)号：US07868608B2

    公开(公告)日：2011-01-11

    申请号：US12420089

    申请日：2009-04-08

    申请人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    发明人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    IPC分类号： G01R31/28

    CPC分类号： G01R31/026 ,  G01R31/043 ,  G01R31/2812 ,  H05K3/341

    摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.

    摘要翻译： 设备可以包括用于连接到印刷电路板的电流源。 该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。 另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。 热监测模块可用于识别不正确的物理连接。

    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT
    7.
    发明申请
    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
    具有条带划分的参考平面电路的电路制造和设计技术

    公开(公告)号：US20100261346A1

    公开(公告)日：2010-10-14

    申请号：US12823316

    申请日：2010-06-25

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H01L21/768 ,  G06F17/50

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持 信号路径导体。

    Detecting Open Ground Connections in Surface Mount Connectors
    8.
    发明申请
    Detecting Open Ground Connections in Surface Mount Connectors 失效
    检测表面贴装连接器中的开放接地连接

    公开(公告)号：US20100259289A1

    公开(公告)日：2010-10-14

    申请号：US12420089

    申请日：2009-04-08

    申请人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    发明人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    IPC分类号： G01R31/02 ,  H01L25/00

    CPC分类号： G01R31/026 ,  G01R31/043 ,  G01R31/2812 ,  H05K3/341

    摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.

    摘要翻译： 设备可以包括用于连接到印刷电路板的电流源。 该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。 另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。 热监测模块可用于识别不正确的物理连接。

    Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density
    9.
    发明授权
    Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density 有权
    多层电路衬底制造和设计方法提供改进的传输线完整性和增加的路由密度

    公开(公告)号：US08624297B2

    公开(公告)日：2014-01-07

    申请号：US12579517

    申请日：2009-10-15

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H01L27/10 ,  H01L21/4763

    CPC分类号： H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

    摘要： An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

    摘要翻译： 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

    Circuit manufacturing and design techniques for reference plane voids with strip segment
    10.
    发明授权
    Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
    具有带段的参考平面空隙的电路制造和设计技术

    公开(公告)号：US08625300B2

    公开(公告)日：2014-01-07

    申请号：US13603761

    申请日：2012-09-05

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H05K1/14

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。