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    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
    4.
    发明申请
    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
    通过/ BSM模式优化，可以降低单个和多个芯片模块上的直流梯度和引脚电流密度

    公开(公告)号：US20070022398A1

    公开(公告)日：2007-01-25

    申请号：US11184350

    申请日：2005-07-19

    申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    IPC分类号： G06F17/50 ,  H01L21/00

    CPC分类号： H01L23/49833 ,  G06F17/5068 ,  H01L23/50 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

    摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

    摘要翻译： 通过将两个不同的电压域分配给载体的接触表面的两个分开的区域，同时为两个电压域提供公共电接地来设计诸如集成电路芯片的电子装置的载体。 集成电路芯片可以是具有额定工作电压的微处理器，并且两个电压域的不同电压都在标称工作电压的公差范围内，但是一个电压域与高功率密度区域 微处理器（例如，微处理器内核）并提供略高的电压。 较高的电源电压域优选地具有大于1的电压引脚与接地引脚的比率。

    Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density
    8.
    发明授权
    Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density 有权
    多层电路衬底制造和设计方法提供改进的传输线完整性和增加的路由密度

    公开(公告)号：US08624297B2

    公开(公告)日：2014-01-07

    申请号：US12579517

    申请日：2009-10-15

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H01L27/10 ,  H01L21/4763

    CPC分类号： H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

    摘要： An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

    摘要翻译： 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

    Circuit manufacturing and design techniques for reference plane voids with strip segment
    9.
    发明授权
    Circuit manufacturing and design techniques for reference plane voids with strip segment 失效
    具有带段的参考平面空隙的电路制造和设计技术

    公开(公告)号：US08625300B2

    公开(公告)日：2014-01-07

    申请号：US13603761

    申请日：2012-09-05

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H05K1/14

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules
    10.
    发明申请
    Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules 有权
    高速陶瓷模块的噪声耦合降低和阻抗不连续控制

    公开(公告)号：US20120204141A1

    公开(公告)日：2012-08-09

    申请号：US13449732

    申请日：2012-04-18

    申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

    发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

    摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

    摘要翻译： 一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸 线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。