公开(公告)号：US10361287B2

公开(公告)日：2019-07-23

申请号：US15260986

申请日：2016-09-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Chih Chen ,  Chih-Ming Hsieh ,  Fu-Tsun Tsai ,  Yung-Fa Lee ,  Chih-Mu Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324

Abstract: A method of manufacturing a semiconductor device includes receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.

公开(公告)号：US10312092B2

公开(公告)日：2019-06-04

申请号：US15875244

申请日：2018-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ru-Shang Hsiao ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor structure includes a first layer having a recessed surface, a metal layer disposed above the first layer, and a second layer disposed above the metal layer and confined by the recessed surface. The second layer includes a first lateral side and a second lateral side. A first thickness of the second layer in a middle portion between the first lateral side and the second lateral side is less than a second thickness of at least one of the first lateral side and the second lateral side of the second layer. The metal layer has a same material across an entire range covered by the second layer.

公开(公告)号：US10090392B2

公开(公告)日：2018-10-02

申请号：US14158643

申请日：2014-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Chih Chen ,  Chih-Mu Huang ,  Ling-Sung Wang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L29/45 ,  H01L21/324 ,  H01L23/485 ,  H01L29/165 ,  H01L21/768

Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.

公开(公告)号：US09893150B2

公开(公告)日：2018-02-13

申请号：US15004365

申请日：2016-01-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Chieh Chiang ,  Chih-Kang Chao ,  Chih-Mu Huang ,  Ling-Sung Wang ,  Ru-Shang Hsiao

IPC: H01L29/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.

公开(公告)号：US09892924B2

公开(公告)日：2018-02-13

申请号：US14658667

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ru-Shang Hsiao ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/28114 ,  H01L21/28247 ,  H01L29/42376 ,  H01L29/66545

Abstract: A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface. The metal layer is above a portion of the recessed surface. The second layer is above the metal layer and confined by the recessed surface. The second layer comprises a top surface, a first lateral side and a second lateral side. The etch rate of an etchant with respect to the metal layer is greater than the etch rate of the etchant with respect to the second layer. The thickness of the second layer in the middle of the second layer is less than the thickness of the second layer at the first lateral side or the second lateral side. A method of forming a semiconductor structure is disclosed.

公开(公告)号：US09865731B2

公开(公告)日：2018-01-09

申请号：US14081517

申请日：2013-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/84 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/161 ,  H01L29/6659

Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.

公开(公告)号：US09490345B2

公开(公告)日：2016-11-08

申请号：US14530320

申请日：2014-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-Chih Chen ,  Fu-Tsun Tsai ,  Yung-Fa Lee ,  Ko-Min Lin ,  Chih-Mu Huang ,  Ying-Lang Wang

IPC: H01L29/417 ,  H01L29/45 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L29/165 ,  H01L21/265 ,  H01L21/768

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract translation: 半导体器件包括在衬底上的栅极结构; 与栅极结构相邻的凸起的源极/漏极区域; 以及掺杂区域上的互连插头。 升高的源极/漏极区域包括从衬底的表面升高的顶表面; 以及暴露在顶表面上的掺杂区域。 掺杂区域包括大于凸起源极/漏极区域的任何其它部分的掺杂剂浓度。 互连插头的最底部包括近似于掺杂区域的宽度的宽度。

公开(公告)号：US09217917B2

公开(公告)日：2015-12-22

申请号：US14192225

申请日：2014-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Shang Hsiao ,  I-I Cheng ,  Jia-Ming Huang ,  Jen-Pan Wang ,  Ling-Sung Wang ,  Chih-Mu Huang

IPC: H01L21/76 ,  G03F1/42 ,  H01L23/544 ,  H01L21/027 ,  G06T7/00

CPC classification number: G03F1/42 ,  G06T7/001 ,  G06T2207/30148 ,  G06T2207/30204 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first material formed on a substrate. The first material includes a first alignment mark. The first alignment mark includes alignment lines in at least three directions. The semiconductor device further includes a second material comprising a second alignment mark. The second alignment mark corresponds to the first alignment mark such that when the second alignment mark is aligned with the first alignment mark, the second material is aligned with the first material.

Abstract translation: 半导体器件包括形成在衬底上的第一材料。 第一材料包括第一对准标记。 第一对准标记包括至少三个方向上的对准线。 半导体器件还包括第二材料，其包括第二对准标记。 第二对准标记对应于第一对准标记，使得当第二对准标记与第一对准标记对准时，第二材料与第一材料对准。

公开(公告)号：US09142588B2

公开(公告)日：2015-09-22

申请号：US14525491

申请日：2014-10-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-I Cheng ,  Chih-Mu Huang ,  Pin Chia Su ,  Chi-Cherng Jeng ,  Volume Chien ,  Chih-Kang Chao

IPC: H01L21/32 ,  H01L27/146 ,  H01L27/14 ,  H01L21/82

CPC classification number: H01L27/14645 ,  H01L21/82 ,  H01L23/585 ,  H01L27/14 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract translation: 模具包括第一多个边缘以及模具中的半导体衬底。 半导体衬底包括第一部分，其包括与第一多个边缘中的相应边缘不对准的第二多个边缘。 半导体衬底还包括从第二多个边缘之一延伸到管芯的第一多个边缘之一的第二部分。 第二部分包括连接到第二多个边缘中的一个边缘的第一端和具有与模具的第一多个边缘中的一个边缘对准的边缘的第二端。

公开(公告)号：US20150044810A1

公开(公告)日：2015-02-12

申请号：US14525491

申请日：2014-10-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-I Cheng ,  Chih-Mu Huang ,  Pin Chia Su ,  Chi-Cherng Jeng ,  Volume Chien ,  Chih-Kang Chao

IPC: H01L27/146

CPC classification number: H01L27/14645 ,  H01L21/82 ,  H01L23/585 ,  H01L27/14 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract translation: 模具包括第一多个边缘以及模具中的半导体衬底。 半导体衬底包括第一部分，其包括与第一多个边缘中的相应边缘不对准的第二多个边缘。 半导体衬底还包括从第二多个边缘之一延伸到管芯的第一多个边缘之一的第二部分。 第二部分包括连接到第二多个边缘中的一个边缘的第一端和具有与模具的第一多个边缘中的一个边缘对准的边缘的第二端。