公开(公告)号：US11996283B2

公开(公告)日：2024-05-28

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/40114 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20220359189A1

公开(公告)日：2022-11-10

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20180151427A1

公开(公告)日：2018-05-31

申请号：US15395057

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/535

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US09633832B2

公开(公告)日：2017-04-25

申请号：US15049420

申请日：2016-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US09564511B2

公开(公告)日：2017-02-07

申请号：US14937301

申请日：2015-11-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Shich-Chang Suen

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

Abstract translation: 一种方法包括在晶片的表面上形成晶体管的虚拟栅极，去除虚拟栅极，并将金属材料填充到由去除的虚拟栅极留下的沟槽中。 然后对金属材料进行化学机械抛光（CMP），其中金属材料的剩余部分形成晶体管的金属栅极。 在CMP之后，使用包含氯和氧的氧化 - 蚀刻剂在金属栅极的暴露的顶表面上进行处理。

公开(公告)号：US20150200089A1

公开(公告)日：2015-07-16

申请号：US14152497

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang SUEN ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/28

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract translation: 本公开提供了一种用于形成集成电路（IC）结构的方法。 该方法包括提供金属栅极（MG），形成在MG上的蚀刻停止层（ESL）以及形成在ESL上的电介质层。 该方法还包括蚀刻ESL和介电层以形成沟槽。 暴露在沟槽中的MG的表面被氧化以在MG上形成第一氧化物层。 该方法还包括使用H 3 PO 4溶液去除第一氧化物层。