公开(公告)号：US11322610B2

公开(公告)日：2022-05-03

申请号：US16776544

申请日：2020-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L21/28 ,  H03K17/687 ,  H01L29/10 ,  H01L21/761 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L27/07 ,  H01L29/08 ,  H03K17/12 ,  H01L29/423

Abstract: A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.

公开(公告)号：US11239318B2

公开(公告)日：2022-02-01

申请号：US16846754

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

公开(公告)号：US20210193809A1

公开(公告)日：2021-06-24

申请号：US17197188

申请日：2021-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US10950720B2

公开(公告)日：2021-03-16

申请号：US15790780

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  David LaFonteese

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H02H9/04 ,  H01L29/423 ,  H03K19/0185 ,  H01L29/10 ,  H01L29/40

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

公开(公告)号：US10903320B2

公开(公告)日：2021-01-26

申请号：US16383857

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L29/40 ,  H01L29/778 ,  H01L23/48 ,  H01L29/423 ,  H01L23/482 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US20210005763A1

公开(公告)日：2021-01-07

申请号：US16502108

申请日：2019-07-03

Applicant: Texas Instruments Incorporated

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/02 ,  H01L27/144 ,  H01L31/18 ,  H01L31/0304 ,  H01L25/04 ,  H01L31/103

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

公开(公告)号：US10468324B2

公开(公告)日：2019-11-05

申请号：US15183896

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/48 ,  H01L21/02 ,  H01L23/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

公开(公告)号：US10304719B2

公开(公告)日：2019-05-28

申请号：US15413118

申请日：2017-01-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L27/088 ,  H01L21/761 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/528

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

公开(公告)号：US10192799B2

公开(公告)日：2019-01-29

申请号：US16010654

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: G01R31/28 ,  G01R31/12 ,  H01L27/08 ,  H01L29/41 ,  H01L29/20 ,  H01L29/40 ,  H01L29/06 ,  H01L21/66 ,  H01L27/088 ,  H01L29/417 ,  H01L23/544

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US10163678B2

公开(公告)日：2018-12-25

申请号：US14682823

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3205

Abstract: Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure.