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    SEAL INTEGRAL TYPE PISTON
    31.
    发明申请
    SEAL INTEGRAL TYPE PISTON 审中-公开
    密封整体式活塞

    公开(公告)号：US20090038906A1

    公开(公告)日：2009-02-12

    申请号：US12187711

    申请日：2008-08-07

    申请人： Tomoaki Nishimura ,  Koji Fujii

    发明人： Tomoaki Nishimura ,  Koji Fujii

    IPC分类号： F16D25/06

    CPC分类号： F16D25/12 ,  F16D2048/0212 ,  F16J1/008

    摘要： To maximize pressing area of a clutch pressing portion (121f) in a seal integral type piston (120) having a piston main body (121) and a seal lip (122), a conical step surface (121g) is formed on an outer surface of an outer peripheral cylinder portion (121e), a clutch pressing portion (121f) is provided at an end of the outer peripheral cylinder portion (121e) via the conical step surface (121g), an end of a rubber film (124) extending from a base portion of the seal lip (122) along the outer surface of the outer peripheral cylinder portion (121e) is positioned at the conical step surface (121g), and a large radial width (a pressing area) of the clutch pressing portion (121f) is secured by making a rubber stop at a time of integrally molding the seal lip (122) on the piston main body (121) at the conical step surface (121g).

    摘要翻译： 为了使具有活塞主体（121）和密封唇（122）的密封一体式活塞（120）中的离合器按压部（121f）的按压面积最大化，在外表面 的外周圆筒部（121e），经由圆锥台阶（121g）设置在外周筒部（121e）的端部的离合器按压部（121f），延伸的橡胶膜（124）的端部 沿着外周圆筒部（121e）的外表面的密封唇（122）的基部位于锥形台阶面（121g），离合器按压部的径向宽度（挤压面积） （121f）在所述锥形台阶面（121g）处一体成型所述密封唇（122）到所述活塞主体（121）上时，通过制造橡胶停止来固定所述密封唇（121f）。

    Wafer transfer equipment and semiconductor device manufacturing apparatus using wafer transfer equipment
    33.
    发明授权
    Wafer transfer equipment and semiconductor device manufacturing apparatus using wafer transfer equipment 失效
    晶圆转移设备和使用晶片转移设备的半导体器件制造设备

    公开(公告)号：US07172383B2

    公开(公告)日：2007-02-06

    申请号：US10873301

    申请日：2004-06-23

    申请人： Koji Fujii ,  Tomoaki Takeuchi

    发明人： Koji Fujii ,  Tomoaki Takeuchi

    IPC分类号： B65G65/00

    CPC分类号： H01L21/67781

    摘要： A semiconductor wafer transfer equipment transfers a plurality of semiconductor wafers, held in grooves of carriers in an erected state, to a boat using first and second wafer elevators equipped with a comb-teeth portion and a wafer grip and transfer unit. The first and second wafer elevators correspond to the carriers and the boat and are equipped with a position correction mechanism which corrects positions of comb-teeth openings of comb-teeth members provided on the comb-teeth portion, corresponding to semiconductor wafers housed in the grooves of the carriers.

    摘要翻译： 半导体晶片传送设备使用装配有梳齿部分和晶片夹持和传送单元的第一和第二晶片升降机将保持在竖立状态的载体槽中的多个半导体晶片传送到船上。 第一和第二晶片升降台对应于载体和船，并且配备有位置校正机构，其校正设置在梳齿部分上的梳齿部件的梳齿开口的位置，对应于容纳在凹槽中的半导体晶片 的运营商。

    Preventive film for polarizer and polarizing plate using the same
    34.
    发明授权
    Preventive film for polarizer and polarizing plate using the same 失效
    使用偏光片和偏光板的预防薄膜

    公开(公告)号：US07138703B2

    公开(公告)日：2006-11-21

    申请号：US10498252

    申请日：2002-12-13

    申请人： Norimasa Maida ,  Koji Fujii ,  Go Fukui

    发明人： Norimasa Maida ,  Koji Fujii ,  Go Fukui

    IPC分类号： H01L23/58

    CPC分类号： B32B27/36 ,  B32B7/12 ,  B32B27/08 ,  B32B27/365 ,  B32B2250/03 ,  B32B2250/244 ,  B32B2307/42 ,  B32B2367/00 ,  B32B2369/00 ,  Y10T428/31504 ,  Y10T428/31507 ,  Y10T428/31786 ,  Y10T428/8305

    摘要： A preventive film for a polarizer which comprises a non-oriented two-layer film comprising a polycarbonate film having a glass transition temperature of 100° C. or higher and, laminated on one surface thereof, a polyester him: a preventive film for a polarizer which comprises a non-oriented three-layer comprising a polycarbonate film having a glass transition temperature of 100° C. or higher and a polyester film laminated on one surface thereof and a polybutylene terephthalate film laminated on the other surface thereof and a polarizing pate which uses a polarizing film comprising a polarizer and two sheets of the above film adhered by heating with no use of an adhesive agent to both sides thereof. The preventive film exhibits an extremely small double refraction and is capable of being adhered directly to a polarizer through heating and the polarizing plate can be produced at a low cost.

    摘要翻译： 一种偏振片用防止膜，其特征在于，包括具有玻璃化转变温度为100℃以上的聚碳酸酯膜的非取向的双层膜，并且在其一个表面上层叠聚酯，其为偏振片用防止膜 其包括无取向三层，其包含玻璃化转变温度为100℃以上的聚碳酸酯膜和层叠在其一个表面上的聚酯膜和层压在其另一个表面上的聚对苯二甲酸丁二醇酯膜和偏振片 使用包含偏振片的偏振片和通过加热粘合的两片上述膜，而不使用粘合剂两侧。 预防膜具有非常小的双折射，并且能够通过加热直接粘附到偏振片，并且可以以低成本制造偏振片。

    Picture tube device having lead electrode with a curved shape
    35.
    发明授权
    Picture tube device having lead electrode with a curved shape 失效
    具有弯曲形状的引线电极的显像管装置

    公开(公告)号：US06943491B2

    公开(公告)日：2005-09-13

    申请号：US10340160

    申请日：2003-01-09

    申请人： Masahide Yamauchi ,  Takashi Itoh ,  Koji Fujii

    发明人： Masahide Yamauchi ,  Takashi Itoh ,  Koji Fujii

    IPC分类号： H01J1/02 ,  H01J1/304 ,  H01J29/04 ,  H01J29/46 ,  H01J29/48 ,  H01J29/58

    CPC分类号： H01J29/04 ,  H01J29/481 ,  H01J29/488 ,  H01J2201/30407 ,  H01J2229/481

    摘要： In a picture tube device with a field-emission cold cathode, including a plurality of electron-emitting cathodes, and a lead electrode provided with a plurality of apertures surrounding the plurality of electron-emitting cathodes respectively, a surface of the lead electrode has a curved shape that is convex in an electron emission direction. This makes it possible to obtain a high-resolution and high-performance picture tube device that has an excellent focus performance over an entire beam current.

    摘要翻译： 在具有场致发射冷阴极的显像管装置中，包括多个电子发射阴极，以及分别具有围绕多个电子发射阴极的多个孔的引线电极，所述引线电极的表面具有 在电子发射方向上凸起的弯曲形状。 这使得可以获得在整个束电流上具有优异的聚焦性能的高分辨率和高性能的显像管装置。

    Preventive film for polarizer and polarizing plate using the same
    36.
    发明申请
    Preventive film for polarizer and polarizing plate using the same 失效
    使用偏光片和偏光板的预防薄膜

    公开(公告)号：US20050128613A1

    公开(公告)日：2005-06-16

    申请号：US10498252

    申请日：2002-12-13

    申请人： Norimasa Maida ,  Koji Fujii ,  Go Fukui

    发明人： Norimasa Maida ,  Koji Fujii ,  Go Fukui

    IPC分类号： G02B5/30 ,  B32B27/36 ,  G02F1/1335 ,  G02B5/08

    CPC分类号： B32B27/36 ,  B32B7/12 ,  B32B27/08 ,  B32B27/365 ,  B32B2250/03 ,  B32B2250/244 ,  B32B2307/42 ,  B32B2367/00 ,  B32B2369/00 ,  Y10T428/31504 ,  Y10T428/31507 ,  Y10T428/31786 ,  Y10T428/8305

    摘要： A preventive film for a polarizer which comprises a non-oriented two-layer film comprising a polycarbonate film having a glass transition temperature of 100° C. or higher and, laminated on one surface thereof, a polyester him: a preventive film for a polarizer which comprises a non-oriented three-layer comprising a polycarbonate film having a glass transition temperature of 100° C. or higher and a polyester film laminated on one surface thereof and a polybutylene terephthalate film laminated on the other surface thereof and a polarizing pate which uses a polarizing film comprising a polarizer and two sheets of the above film adhered by heating with no use of an adhesive agent to both sides thereof. The preventive film exhibits an extremely small double refraction and is capable of being adhered directly to a polarizer through heating and the polarizing plate can be produced at a low cost.

    摘要翻译： 一种偏振片用防止膜，其特征在于，包括具有玻璃化转变温度为100℃以上的聚碳酸酯膜的非取向的双层膜，并且在其一个表面上层叠聚酯，其为偏振片用防止膜 其包括无取向三层，其包含玻璃化转变温度为100℃以上的聚碳酸酯膜和层叠在其一个表面上的聚酯膜和层压在其另一个表面上的聚对苯二甲酸丁二醇酯膜和偏振片 使用包含偏振片的偏振片和通过加热粘合的两片上述膜，而不使用粘合剂两侧。 预防膜具有非常小的双折射，并且能够通过加热直接粘附到偏振片，并且可以以低成本制造偏振片。

    Self-timed pipelined datapath system and asynchronous signal control circuit
    37.
    发明授权
    Self-timed pipelined datapath system and asynchronous signal control circuit 有权
    自定时流水线数据通路系统和异步信号控制电路

    公开(公告)号：US06320418B1

    公开(公告)日：2001-11-20

    申请号：US09675151

    申请日：2000-09-29

    申请人： Koji Fujii ,  Takakuni Douseki

    发明人： Koji Fujii ,  Takakuni Douseki

    IPC分类号： H03K19096

    CPC分类号： G06F9/3871 ,  G06F1/32 ,  G06F9/3869

    摘要： A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal. The state change of an active state to an inactive state of the combinational circuit is performed in consideration of the signal propagation time therein, whereby the issue of the request signal with respect to the combinational circuit at the preceding stage is delayed from the time the request signal with respect to the current combinational circuit is issued.

    摘要翻译： 自定时流水线数据路径系统通过精确控制用作其组合电路的多阈值CMOS（MT-CMOS）电路的有功和无效状态来降低功耗。 MT-CMOS电路包括低阈值的逻辑电路和由用于控制对逻辑电路的馈电的高阈值晶体管形成的功率控制电路。 自定时流水线数据路径系统包括：流水线数据路径电路，包括多个数据处理级，每个数据处理级具有用于处理输入数据的组合电路和连接到组合电路的输入侧的寄存器; 以及异步信号控制电路，其响应于请求信号控制到流水线数据路径电路中的每个寄存器的数据传输。 考虑到其中的信号传播时间，执行组合电路的有效状态到无效状态的状态改变，由此相对于前一级的组合电路的请求信号的发出从请求的时间延迟 发出相对于当前组合电路的信号。

    Dynamic logic circuit and self-timed pipelined datapath system
    38.
    发明授权
    Dynamic logic circuit and self-timed pipelined datapath system 失效
    动态逻辑电路和自定时流水线数据通路系统

    公开(公告)号：US06225827B1

    公开(公告)日：2001-05-01

    申请号：US09033913

    申请日：1998-03-03

    申请人： Koji Fujii ,  Takakuni Douseki

    发明人： Koji Fujii ,  Takakuni Douseki

    IPC分类号： H03K19096

    CPC分类号： H03K19/0966

    摘要： A dynamic logic circuit comprising a plurality of unit dynamic logic circuits sequentially coupled in a multiple-stage fashion, each of which unit dynamic logic circuits including: a logic circuit portion formed by one or more than one MOS transistors; a first MOS transistor for a precharging or a pre-discharging operation with respect to the logic circuit; and a second MOS transistor to enable the logic circuit a discharging or a charging operation; wherein the MOS transistors composing the logic circuit portion are configured by low-threshold MOS transistors; and the second MOS transistor to enable the discharging or charging operation is composed of a high-threshold MOS transistor. The dynamic circuit is applied to a plural stage of combinational circuits in a self-timed pipelined datapath system, whereby a static leakage current at charging or pre-discharging operation can be reduced, resulting in decrease of power dissipation.

    摘要翻译： 一种动态逻辑电路，包括以多级方式顺序耦合的多个单位动态逻辑电路，其中每一单位动态逻辑电路包括：由一个或多于一个MOS晶体管形成的逻辑电路部分; 用于相对于逻辑电路进行预充电或预放电操作的第一MOS晶体管; 以及使所述逻辑电路能够进行放电或充电操作的第二MOS晶体管; 其中构成逻辑电路部分的MOS晶体管由低阈值MOS晶体管构成; 并且能够进行放电或充电操作的第二MOS晶体管由高阈值MOS晶体管构成。 动态电路在自定时流水线数据路径系统中应用于多级组合电路，从而可以减少充电或预放电操作时的静态泄漏电流，从而降低功耗。

    Developing bias control device capable of properly controlling developing bias voltage
    39.
    发明授权
    Developing bias control device capable of properly controlling developing bias voltage 有权
    开发能够正确控制显影偏压的偏置控制装置

    公开(公告)号：US08032042B2

    公开(公告)日：2011-10-04

    申请号：US12392157

    申请日：2009-02-25

    申请人： Koji Fujii

    发明人： Koji Fujii

    IPC分类号： G03G15/06

    CPC分类号： G03G15/08 ,  G03G15/0121 ,  G03G2215/0129

    摘要： Upon receiving a request to control developing bias voltage, first and second square-wave signal output units output first and second square-wave signals, respectively. When a rising edge of the first square-wave signal coincides with a rising edge of the second square-wave signal, the rising edge of the second square-wave signal is advanced with respect to the rising edge of the first square-wave signal. When a falling edge of the first square-wave signal coincides with a falling edge of the second square-wave signal, the falling edge of the second square-wave signal is delayed with respect to the falling edge of the first square-wave signal. Subsequently, a voltage-controlling square-wave signal for controlling developing bias voltage is generated based on the first and second square-wave signals.

    摘要翻译： 在接收到控制显影偏压的请求时，第一和第二方波信号输出单元分别输出第一和第二方波信号。 当第一方波信号的上升沿与第二方波信号的上升沿一致时，第二方波信号的上升沿相对于第一方波信号的上升沿而前进。 当第一方波信号的下降沿与第二方波信号的下降沿一致时，第二方波信号的下降沿相对于第一方波信号的下降沿被延迟。 随后，基于第一和第二方波信号产生用于控制显影偏压的电压控制方波信号。

    Pillar construction for vehicle
    40.
    发明授权
    Pillar construction for vehicle 有权
    车辆支柱施工

    公开(公告)号：US07614687B2

    公开(公告)日：2009-11-10

    申请号：US12055044

    申请日：2008-03-25

    申请人： Takuo Nakamura ,  Hayami Nakagawa ,  Junichi Yanase ,  Hiroyuki Seino ,  Hideki Ito ,  Koji Fujii ,  Setoshi Yanagimoto ,  Masato Onodera ,  Fumiya Amano

    发明人： Takuo Nakamura ,  Hayami Nakagawa ,  Junichi Yanase ,  Hiroyuki Seino ,  Hideki Ito ,  Koji Fujii ,  Setoshi Yanagimoto ,  Masato Onodera ,  Fumiya Amano

    IPC分类号： B60N99/00

    CPC分类号： B62D25/04

    摘要： An upper member of a pillar has a substantially U-shaped cross section, and includes first side walls extending substantially in a transverse direction of the vehicle at least at a lower portion, and a connecting plate at a lower end while keeping the U-shaped cross section. A lower member includes a mounting plate opposed to the connecting plate at a lower portion being lower than an upper end, and second side walls extending substantially in the transverse direction at both end portions of the mounting plate in a longitudinal direction of the vehicle. The connecting plate and the mounting plate are welded to each other in a state that they are in abutment with each other, and the first side walls and the second side walls are joined to each other, and the upper member and the lower member are integrally fixed to each other.

    摘要翻译： 柱的上部构件具有大致U形的横截面，并且包括至少在下部基本上在车辆的横向方向上延伸的第一侧壁和在下端处的连接板，同时保持U形 横截面。 下部构件包括在下部处的连接板相对于下端的安装板，以及在车辆的纵向方向上在安装板的两个端部处基本上沿横向方向延伸的第二侧壁。 连接板和安装板在它们彼此邻接的状态下彼此焊接，并且第一侧壁和第二侧壁彼此接合，并且上部构件和下部构件一体地 相互固定