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公开(公告)号：US20100038795A1
公开(公告)日：2010-02-18
申请号：US12542540
申请日：2009-08-17
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76816 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.
摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式
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32.发明申请METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM 有权用于制造半导体器件的方法和用于存储图案尺寸设置程序的计算机可读介质公开(公告)号：US20090258503A1
公开(公告)日：2009-10-15
申请号：US12403740
申请日：2009-03-13
IPC分类号： H01L21/306
CPC分类号： H01L21/0337
摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.
摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。
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公开(公告)号：US20060197136A1
公开(公告)日：2006-09-07
申请号：US11346293
申请日：2006-02-03
申请人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11517
摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
摘要翻译： 根据本发明，实现了高可靠性的NAND型闪速存储器。 它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成 接线层。
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34.发明申请Lithography simulation method, program and semiconductor device manufacturing method 失效平版印刷模拟方法，程序和半导体器件制造方法公开(公告)号：US20070277146A1
公开(公告)日：2007-11-29
申请号：US11802615
申请日：2007-05-24
申请人： Masaki Satake , Hiromitsu Mashita , Satoshi Tanaka
发明人： Masaki Satake , Hiromitsu Mashita , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F7/705 , G03F7/70666
摘要： A lithography simulation method which predicts the result that a pattern formed on a mask is transferred onto a sample by use of a simulation based on pattern data of the mask includes subjecting a mask layout containing a pattern whose periodicity is disturbed to the simulation. At this time, a calculation area of pattern data used for the simulation is set to an integral multiple of minimum periodic length of the mask layout.
摘要翻译： 通过使用基于掩模的图案数据的模拟将掩模上形成的图案转移到样本上的结果的光刻仿真方法包括对包含周期性被扰乱的图案的掩模布局进行模拟。 此时，将用于模拟的图案数据的计算区域设置为掩模布局的最小周期长度的整数倍。
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公开(公告)号：US08243491B2
公开(公告)日：2012-08-14
申请号：US12884378
申请日：2010-09-17
申请人： Toshiki Hisada , Hiromitsu Mashita
发明人： Toshiki Hisada , Hiromitsu Mashita
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C7/18 , G11C2207/002 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.
摘要翻译： 根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。 位线包括顺序排列的第一，第二，第三和第四位线。 第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。 第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。 第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。 第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。
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公开(公告)号：US20120001331A1
公开(公告)日：2012-01-05
申请号：US13051652
申请日：2011-03-18
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L21/76816 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.
摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。
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公开(公告)号：US20080137421A1
公开(公告)日：2008-06-12
申请号：US11943771
申请日：2007-11-21
CPC分类号： H01L27/0207 , G11C5/025 , H01L27/115 , Y10T428/24802
摘要： In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
摘要翻译： 在图案布局中，包括具有均匀重复的图案组的第一装置图案，该第一装置图案具有第一线和平行于一个花柱形成的第一间隔，并且以恒定间距均匀地布置，并且具有第一线和第一线的不均匀重复的图案组 以及与其非排列方向上的非均匀重复图形组的端部相邻排列的第二装置图案，并且具有第二线和第二空间，第二线和第二空间的宽度大于第一线和第一线的宽度 不均匀重复图案组的空间，使不均匀重复图案组的第一线和第一空间的宽度的至少一部分大于第一线的宽度或第一空间的第一空间的宽度 均匀重复模式组。
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公开(公告)号：US08283791B2
公开(公告)日：2012-10-09
申请号：US13051652
申请日：2011-03-18
CPC分类号： H01L21/76816 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.
摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。
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公开(公告)号：US20110176347A1
公开(公告)日：2011-07-21
申请号：US12884378
申请日：2010-09-17
申请人： Toshiki HISADA , Hiromitsu Mashita
发明人： Toshiki HISADA , Hiromitsu Mashita
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C7/18 , G11C2207/002 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.
摘要翻译： 根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。 位线包括顺序排列的第一，第二，第三和第四位线。 第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。 第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。 第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。 第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。
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公开(公告)号：US20120020158A1
公开(公告)日：2012-01-26
申请号：US13187000
申请日：2011-07-20
申请人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
发明人： Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
CPC分类号： H01L27/11521
摘要： A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).
摘要翻译： 存储单元阵列包括沿第一方向布置的存储器串。 字线和选择栅极线在垂直于第一方向的第二方向上延伸。 选择栅极线也沿第二方向延伸。 字线在第一方向上具有第一线宽度并且以它们之间的第一距离布置。 选择栅极线包括在第一方向上的第一互连，第一互连具有大于第一线宽的第二线宽，以及从第一互连的端部延伸的第二互连，第二互连具有第三线宽 与第一行宽度相同。 与选择栅极线相邻的第一字线布置成具有到第二互连的第二距离，第二距离为（4N + 1）倍于第一距离（N为1或更大的整数）。
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