公开(公告)号：US08274826B2

公开(公告)日：2012-09-25

申请号：US12838867

申请日：2010-07-19

申请人： Toshifumi Hashimoto ,  Noboru Shibata ,  Toshiki Hisada ,  Tsuneo Inaba

发明人： Toshifumi Hashimoto ,  Noboru Shibata ,  Toshiki Hisada ,  Tsuneo Inaba

IPC分类号： G11C16/04

CPC分类号： G11C16/06

摘要： According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.

摘要翻译： 根据一个实施例，NAND型闪速存储器包括设置在第一和第二存储器平面之间的第一传输晶体管，第一传输晶体管的第一电位传输端共同连接到第一NAND块中的第一字线，第二字 配置在第三NAND块中的第二转移晶体管，设置在第一存储器平面的第一端的第二转移晶体管，第二转移晶体管的第一电位转移端连接到第二NAND块中的第三字线，以及第三转移晶体管 设置在第二存储器平面的第二端，第三传输晶体管的第一电位传输端连接到第四NAND块中的第四字线。

公开(公告)号：US07721239B2

公开(公告)日：2010-05-18

申请号：US11624386

申请日：2007-01-18

申请人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

发明人： Yoshiko Kato ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi ,  Toshiki Hisada

IPC分类号： G06F17/50

CPC分类号： G11C16/0483 ,  G11C16/08 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11529

摘要： A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

摘要翻译： 根据本发明的半导体集成电路包括由元件构成的单元阵列，具有布置在单元阵列上的线和空间的图案的导线，形成在导线上方的连接线，以及将导线 到连接线。 导线的一端侧从导体线之一顺序离开电池阵列的端部，接触孔布置在导线的一端侧，接触孔的尺寸较大 比导线的宽度大。

公开(公告)号：US06801144B2

公开(公告)日：2004-10-05

申请号：US10678742

申请日：2003-10-02

申请人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

发明人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

IPC分类号： H03M900

CPC分类号： G11C7/1036

摘要： An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

摘要翻译： 输入/输出电路输入/输出串行数据。 寄存器部分包括第一和第二寄存器。 第一个寄存器将串行数据转换为并行数据。 第二个寄存器将并行数据转换为串行数据。 当串行数据被转换成并行数据时，第一控制信号为每个位提供转换定时。 当并行数据被转换成串行数据时，第二控制信号为每个位提供转换定时。 信号发生电路控制第一控制信号的上升或下降的定时，并设置哪个存储单元应存储串行数据的每个位的值，并且控制第二控制信号的上升或下降的定时，以及 将串行数据的值的数量设置为从存储器单元读取的并行数据的每个位的值。

公开(公告)号：US06498741B2

公开(公告)日：2002-12-24

申请号：US09746890

申请日：2000-12-21

申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

摘要翻译： 提供一种半导体存储器件，其确保存储器数据传输时间和高速操作的对称性，并且具有大的写入/读取操作裕度，而不需要增加芯片面积。 通过在半导体芯片的垂直方向上的中间放置一个水平长的外围电路部分，将垂直长的移位寄存器部分设置在周边电路部分的上下方向并垂直于外围电路部分，并使存储器核心和移位寄存器装置在 水平方向，可以使存储器芯和移位寄存器部分之间的数据/信号线短，并且可以保持互连的对称性，这允许实现高速和大面积的半导体存储器件。 另外，通过将每个对应于数据块的移位寄存器堆叠并选择堆叠移位寄存器的顺序，使得外围电路与移位之间的互连长度可以获得更快的半导体存储器 寄存器被最小化。

公开(公告)号：US06198649B1

公开(公告)日：2001-03-06

申请号：US09460641

申请日：1999-12-15

申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

公开(公告)号：US5914505A

公开(公告)日：1999-06-22

申请号：US706394

申请日：1996-08-30

申请人： Toshiki Hisada ,  Hiroyuki Koinuma

发明人： Toshiki Hisada ,  Hiroyuki Koinuma

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/10 ,  G11C11/409 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10

CPC分类号： G11C7/1078 ,  G11C5/14 ,  H01L27/0251 ,  H01L27/0928 ,  H01L27/105

摘要： A semiconductor integrated circuit includes an input circuit for receiving an input signal from the outside, an internal circuit connected to the input circuit, an output circuit connected to the internal circuit for outputting an output signal to the outside, a power supply line connected to each of the circuits, a power supply terminal connected to the power supply line, a first ground conductor connected to the input circuit, a second ground conductor separated from the first ground conductor and connected to the internal circuit, a first ground terminal connected to the first ground conductor and a second ground terminal connected to the second ground conductor. Because of the provision of the ground conductor exclusively for the input circuit, malfunction of the input circuit due to power supply fluctuations is prevented and an operation margin is increased.

摘要翻译： 半导体集成电路包括用于从外部接收输入信号的输入电路，连接到输入电路的内部电路，连接到内部电路以将输出信号输出到外部的输出电路，连接到每一个的电源线 连接到电源线的电源端子，连接到输入电路的第一接地导体，与第一接地导体分离并连接到内部电路的第二接地导体，连接到第一接地导体的第一接地端子 接地导体和连接到第二接地导体的第二接地端子。 由于专门为输入电路提供接地导体，所以防止了由于电源波动引起的输入电路的故障，并增加了操作余量。

公开(公告)号：US5734292A

公开(公告)日：1998-03-31

申请号：US520773

申请日：1995-08-30

申请人： Yutaka Shirai ,  Toshiki Hisada ,  Hiroyuki Koinuma

发明人： Yutaka Shirai ,  Toshiki Hisada ,  Hiroyuki Koinuma

IPC分类号： G11C11/407 ,  G05F3/24 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4094 ,  G05F1/10

CPC分类号： G11C11/4074 ,  G05F3/242 ,  G11C11/4094 ,  G11C5/147

摘要： The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.

摘要翻译： NMOS晶体管的栅极接收参考电位，源极连接到输出节点。 负载元件设置在该晶体管的漏极和电源之间。 第一和第二反相器电路顺序地反转NMOS晶体管的漏极电位并将其传送到PMOS晶体管的栅极。 PMOS晶体管的源极连接到电源，漏极连接到输出节点。 当输出节点的电位变得低于参考电位时，PMOS晶体管被激活直到来自反相器电路的输出反转，从而以大的电流对输出节点充电。

公开(公告)号：US5654935A

公开(公告)日：1997-08-05

申请号：US528700

申请日：1995-09-15

申请人： Toshiki Hisada ,  Hiroyuki Koinuma

发明人： Toshiki Hisada ,  Hiroyuki Koinuma

IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C8/18

摘要： A semiconductor memory includes a plurality of memory cells aligned in rows and columns, a plurality of bit lines respectively connected to the columns of the plurality of memory cells, a plurality of switch circuits each having one end connected to a corresponding one of the plurality of bit lines, the plurality of switch circuits being selectively turned on in accordance with a column address signal input from an outside to identify each of the columns, a data line to which the other end of each of the plurality of switch circuits is commonly connected, a pulse generation circuit for detecting a change in level of the column address signal with respect to first and second circuit thresholds different from each other to generate a pulse signal, the first circuit threshold being used for detecting a change in address signal from one level to the other level, and the second circuit threshold being used for detecting a change in address signal from the other level to one level, and a data detection circuit, connected to the data line and controlled by the pulse signal generated in accordance with the pulse generation circuits, for amplifying a potential of the data line to detect data.

摘要翻译： 一种半导体存储器包括以行和列排列的多个存储单元，分别连接到多个存储单元的列的多个位线，多个开关电路，每个开关电路的一端连接到多个存储单元 所述多个开关电路根据从外部输入的列地址信号选择性地导通，以识别每个所述列，所述多个开关电路中的每一个的另一端共同连接的数据线， 用于检测相对于彼此不同的第一和第二电路阈值的列地址信号的电平变化以产生脉冲信号的脉冲发生电路，所述第一电路阈值用于检测地址信号从一个电平变化到 另一个电平，第二电路阈值被用于检测从另一个电平到一个电平的地址信号的变化，以及一个数据 检测电路，连接到数据线并由根据脉冲发生电路产生的脉冲信号控制，用于放大数据线的电位以检测数据。

公开(公告)号：US08283791B2

公开(公告)日：2012-10-09

申请号：US13051652

申请日：2011-03-18

申请人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

发明人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76816 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

公开(公告)号：US20110176347A1

公开(公告)日：2011-07-21

申请号：US12884378

申请日：2010-09-17

申请人： Toshiki HISADA ,  Hiromitsu Mashita

发明人： Toshiki HISADA ,  Hiromitsu Mashita

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C7/18 ,  G11C2207/002 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.

摘要翻译： 根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。 位线包括顺序排列的第一，第二，第三和第四位线。 第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。 第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。 第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。 第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。