公开(公告)号：US20220278213A1

公开(公告)日：2022-09-01

申请号：US17743992

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

公开(公告)号：US11430789B2

公开(公告)日：2022-08-30

申请号：US17104351

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure includes a base layer, an isolating layer over the base layer, and a stack of channel layers and first sacrificial layers alternately stacked over the isolating layer. The method further includes forming an isolation structure adjacent to sidewalls of the fin structure, wherein a top surface of the isolation structure is above a bottom surface of the isolating layer and below a top surface of the isolating layer. The method further includes depositing a second sacrificial layer over the isolation structure and over the sidewalls of the fin structure; etching the second sacrificial layer and the fin structure to form two source/drain trenches, wherein the source/drain trenches expose the base layer; partially removing the first and the second sacrificial layers through the source/drain trenches to form gaps; and depositing a dielectric spacer in the gaps.

公开(公告)号：US11328963B2

公开(公告)日：2022-05-10

申请号：US16947398

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Shi Ning Ju ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US11322493B2

公开(公告)日：2022-05-03

申请号：US16929592

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Huan-Chieh Su ,  Kuo-Cheng Chiang

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/786

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

公开(公告)号：US20220115510A1

公开(公告)日：2022-04-14

申请号：US17069344

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Lin-Yu Huang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

公开(公告)号：US20220069117A1

公开(公告)日：2022-03-03

申请号：US17112293

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.

公开(公告)号：US20210408247A1

公开(公告)日：2021-12-30

申请号：US17091159

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

公开(公告)号：US11158512B2

公开(公告)日：2021-10-26

申请号：US16895464

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Zhi-Chang Lin ,  Wei-Hao Wu ,  Huan-Chieh Su ,  Chung-Wei Hsu ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: A FinFET device structure is provided. The FinFET device structure includes a substrate, a fin structure formed over the substrate, and an isolation structure formed over the substrate. The fin structure protrudes from the isolation structure. The FinFET device structure further includes a fin isolation structure formed over the isolation structure and a metal gate structure formed over the fin structure and the fin isolation structure.

公开(公告)号：US20210167193A1

公开(公告)日：2021-06-03

申请号：US17174990

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/308

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

公开(公告)号：US20210134944A1

公开(公告)日：2021-05-06

申请号：US16916466

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L27/118 ,  H01L27/092 ,  H01L21/8238

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.