公开(公告)号：US10991819B2

公开(公告)日：2021-04-27

申请号：US16132793

申请日：2018-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/43

Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

公开(公告)号：US20210119011A1

公开(公告)日：2021-04-22

申请号：US17114715

申请日：2020-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L23/31 ,  H01L29/78

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

公开(公告)号：US20200075314A1

公开(公告)日：2020-03-05

申请号：US16395673

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Kuei-Ming Chen

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L23/00 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards a group III-V device including a seed buffer layer that is doped and that is directly on a silicon substrate. In some embodiments, the group III-V device includes the silicon substrate, the seed buffer layer, a heterojunction structure, a pair of source/drain electrodes, and a gate electrode. The seed buffer layer overlies and directly contacts the silicon substrate. Further, the seed buffer layer includes a group III nitride (e.g., AlN) that is doped with p-type dopants. The heterojunction structure overlies the seed buffer layer. The source/drain electrodes overlie the heterojunction structure. The gate electrode overlies the heterojunction structure, laterally between the source/drain electrodes. The p-type dopants prevent the formation of a two-dimensional hole gas (2DHG) in the silicon substrate, along an interface at which the silicon substrate and the seed buffer layer directly contact.

公开(公告)号：US10014402B1

公开(公告)日：2018-07-03

申请号：US15434325

申请日：2017-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/10 ,  H01L29/207 ,  H01L29/417 ,  H01L23/31 ,  H01L21/02

Abstract: A high electron mobility transistor (HEMT) device structure is provided. The HEMT device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The HEMT device structure also includes a gate structure formed over the active layer, and the gate structure includes: a p-doped gallium nitride (p-GaN) layer or a p-doped aluminum gallium nitride (p-GaN) layer formed over the active layer, and a portion of the p-GaN layer or p-AlGaN layer has a stepwise or gradient doping concentration. The HEMT device structure also includes a gate electrode over the p-GaN layer or p-AlGaN layer.

公开(公告)号：US09620362B2

公开(公告)日：2017-04-11

申请号：US14699046

申请日：2015-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/02694 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02617 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

公开(公告)号：US20160240679A1

公开(公告)日：2016-08-18

申请号：US14620399

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7849 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786

Abstract: A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided.

Abstract translation: 提供了具有多应变层超晶格（SLS）结构的晶体管。 第一应变层超晶格（SLS）层布置在衬底上。 第一缓冲层布置在第一SLS层之上，并且包括被配置为增加第一缓冲层的电阻的掺杂剂。 在第一缓冲层上布置第二SLS层。 第二缓冲层布置在第二SLS层上，并且包括被配置为增加第二缓冲层的电阻的掺杂剂。 沟道层布置在第二缓冲层上。 有源层布置在通道层上方并直接邻接通道层。 通道和有源层共同定义异质结。 还提供了制造晶体管的方法。

公开(公告)号：US20140209920A1

公开(公告)日：2014-07-31

申请号：US13755058

申请日：2013-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/0843 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/7787

Abstract: The present disclosure relates to a channel layer of bi-layer of gallium nitride (GaN) within a HEMT. A first breakdown voltage layer of GaN is disposed beneath an active layer of the HEMT. A second breakdown voltage layer of GaN is disposed beneath the first breakdown voltage layer, wherein the first resistivity value is less than the second resistivity value. An increased resistivity of the second breakdown voltage layer results from an increased concentration of carbon dopants which increases the breakdown voltage in the second breakdown voltage layer, but can degrade the crystal structure. To alleviate this degradation, a crystal adaptation layer is disposed beneath the second breakdown voltage layer and configured to lattice-match to the second breakdown voltage layer of GaN. As a result, the HEMT achieves a high breakdown voltage without any associated degradation to the first breakdown voltage layer, wherein a channel of the HEMT resides.

Abstract translation: 本公开涉及HEMT内的氮化镓（GaN）双层的沟道层。 GaN的第一击穿电压层设置在HEMT的有源层的下方。 GaN的第二击穿电压层设置在第一击穿电压层的下方，其中第一电阻率值小于第二电阻率值。 第二击穿电压层的电阻率增加是由于增加了第二击穿电压层中的击穿电压但增加了晶体结构的碳掺杂剂的浓度增加。 为了减轻这种劣化，晶体适配层设置在第二击穿电压层之下，并被配置为与GaN的第二击穿电压层进行晶格匹配。 结果，HEMT实现了高的击穿电压，而没有与第一击穿电压层相关的任何相关的劣化，其中HEMT的通道驻留。

公开(公告)号：US20140209918A1

公开(公告)日：2014-07-31

申请号：US13749819

申请日：2013-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/20 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device.

Abstract translation: 本公开涉及具有GaN和氮化铝（AlN）交替层的复合氮化镓层的氮化镓（GaN）晶体管器件。 在一些实施例中，GaN晶体管器件具有设置在半导体衬底之上的第一GaN层。 AlN层间设置在第一GaN层上。 第二GaN层设置在AlN层间。 AlN层间层允许GaN层的厚度在连续的GaN层上增加，减轻了GaN衬底的弯曲和破裂，同时改善了所公开的GaN器件的击穿电压。