公开(公告)号：US20210273103A1

公开(公告)日：2021-09-02

申请号：US16945394

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.

公开(公告)号：US12211749B2

公开(公告)日：2025-01-28

申请号：US17815302

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view. Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

公开(公告)号：US12087842B2

公开(公告)日：2024-09-10

申请号：US18336788

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/7853 ,  H01L21/0214 ,  H01L21/0228

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US20240266416A1

公开(公告)日：2024-08-08

申请号：US18617746

申请日：2024-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsieh Wong ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78696

Abstract: Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.

公开(公告)号：US11799002B2

公开(公告)日：2023-10-24

申请号：US17199933

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Po Lin ,  Wei-Yang Lee ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Jiun-Ming Kuo

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.

公开(公告)号：US11791402B2

公开(公告)日：2023-10-17

申请号：US17320428

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Wei-Yuan Lu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66553 ,  H01L29/7851

Abstract: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.

公开(公告)号：US11631736B2

公开(公告)日：2023-04-18

申请号：US16901631

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522

Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

公开(公告)号：US11575047B2

公开(公告)日：2023-02-07

申请号：US17318362

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3213

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

公开(公告)号：US20220384660A1

公开(公告)日：2022-12-01

申请号：US17883234

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

公开(公告)号：US11515211B2

公开(公告)日：2022-11-29

申请号：US16887273

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/82 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08

Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.