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    Method and system for detecting hotspots in semiconductor wafer
    32.
    发明授权
    Method and system for detecting hotspots in semiconductor wafer 有权

    公开(公告)号：US10102615B2

    公开(公告)日：2018-10-16

    申请号：US15378482

    申请日：2016-12-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Hao Cheng ,  Peng-Ren Chen ,  Chih-Chiang Tu

    IPC: G06K9/00 ,  G06T7/00

    Abstract: Methods and system for detecting hotspots in semiconductor wafer are provided. At least one semiconductor wafer is inspected to detect a plurality of hotspots of each die in the semiconductor wafer, wherein each of the hotspots has defect coordinates in a layout of the die. The hotspots of the dies are stacked in the layout according to the defect coordinates of the hotspots. A common pattern is obtained according to the stacked hotspots corresponding to a location with specific coordinates in the layout. It is determined whether the common pattern is a known pattern having an individual identification (ID) code. A new ID code is assigned to the common pattern when the common pattern is an unknown pattern.

    Apparatus and method for e-beam writing
    34.
    发明授权
    Apparatus and method for e-beam writing 有权
    电子束写入的装置和方法

    公开(公告)号：US09367661B2

    公开(公告)日：2016-06-14

    申请号：US14477285

    申请日：2014-09-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jia-Guei Jou ,  Yi-Chiuan Luo ,  Chih-Chung Huang ,  Chi-Ming Tsai ,  Chih-Chiang Tu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value.

    Abstract translation: 一种制备掩模数据的方法，该方法开始于对设计布局进行逻辑运算，并且对设计布局执行光学邻近校正（OPC）以形成OPC特征。 OPC特征在线上具有第一点动和第二点动，并且第一点动大于第二点动宽度。 如果第一点动到第二点动的宽度比小于预定值，则OPC特征被调整大小以形成调整大小的第一点动和在线上的调整大小的第二点动。

    APPARATUS AND METHOD FOR E-BEAM WRITING
    35.
    发明申请
    APPARATUS AND METHOD FOR E-BEAM WRITING 有权
    电子束写作的装置和方法

    公开(公告)号：US20160070843A1

    公开(公告)日：2016-03-10

    申请号：US14477285

    申请日：2014-09-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jia-Guei JOU ,  Yi-Chiuan Luo ,  Chih-Chung Huang ,  Chi-Ming Tsai ,  Chih-Chiang Tu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value.

    Abstract translation: 一种制备掩模数据的方法，该方法开始于对设计布局进行逻辑运算，并且对设计布局执行光学邻近校正（OPC）以形成OPC特征。 OPC特征在线上具有第一点动和第二点动，并且第一点动大于第二点动宽度。 如果第一点动到第二点动的宽度比小于预定值，则OPC特征被调整大小以形成调整大小的第一点动和在线上的调整大小的第二点动。

    Photovoltaic device
    36.
    发明授权
    Photovoltaic device 有权
    光伏装置

    公开(公告)号：US09202947B2

    公开(公告)日：2015-12-01

    申请号：US14032244

    申请日：2013-09-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Tu ,  Chun-Lang Chen

    IPC: H01L31/00 ,  H01L31/0224 ,  H01L31/0392 ,  H01L31/0749 ,  H01L31/18 ,  H01L31/0463

    CPC classification number: H01L31/022425 ,  H01L31/03923 ,  H01L31/03928 ,  H01L31/0463 ,  H01L31/0749 ,  H01L31/18 ,  Y02E10/541 ,  Y02P70/521

    Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.

    Abstract translation: 公开了一种光电器件制造方法。 方法包括使用纳米压印技术制造光伏电池来限定光伏器件的单个电池单元。 所述方法可以包括提供基底; 在所述衬底上形成第一导电层; 使用纳米压印和蚀刻工艺在第一导电层中形成第一凹槽; 在所述第一导电层上形成吸收层，所述吸收层填充在所述第一槽中; 使用纳米压印法在吸收层中形成第二凹槽; 在所述吸收层上形成第二导电层，所述第二导电层填充在所述第二槽中; 以及在所述第二导电层和所述吸收层中形成第三凹槽，从而限定光伏电池单元。

    MASK OVERLAY CONTROL
    37.
    发明申请
    MASK OVERLAY CONTROL 有权
    掩蔽覆盖控制

    公开(公告)号：US20150227038A1

    公开(公告)日：2015-08-13

    申请号：US14696596

    申请日：2015-04-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Jong-Yuh Chang ,  Chien-Chih Chen ,  Chen-Shao Hsu

    IPC: G03F1/22 ,  G03F9/00

    CPC classification number: G03F7/70783 ,  G03F1/22 ,  G03F1/70 ,  G03F9/7069

    Abstract: In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.

    Abstract translation: 在一些实施例中，掩模图案形成系统包括被配置为存储集成电路掩模布局的电子存储器。 计算工具确定用于将集成电路掩模布局写入物理掩模的多个辐射照射。 计算工具还确定了由于在将集成电路掩模布局写入物理掩模中使用的辐射照射的数量而导致物理掩模的预期热膨胀的缩放因子。 ebeam或激光写入工具根据缩放因子和使用辐射数量将集成电路掩模布局写入物理掩模。

    Mask blank for scattering effect reduction
    38.
    发明授权
    Mask blank for scattering effect reduction 有权
    掩模空白用于散射效应的降低

    公开(公告)号：US08999611B2

    公开(公告)日：2015-04-07

    申请号：US13788105

    申请日：2013-03-07

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Jong-Yuh Chang ,  Chien-Chih Chen ,  Chen-Shao Hsu

    IPC: G03F1/20

    CPC classification number: G03F1/20

    Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.

    Abstract translation: 一些实施例涉及形成用于深紫外光刻工艺（例如，具有193nm的波长的曝光辐射）的光掩模的方法。 该方法提供用于深紫外光刻工艺的掩模坯料。 掩模坯料具有透明基板，位于透明基板上方的非晶隔离层以及位于非晶隔离层之上的光致抗蚀剂层。 通过使用电子束选择性去除光致抗蚀剂层的部分来对光致抗蚀剂层进行构图。 随后根据图案化的光致抗蚀剂层蚀刻非晶隔离层以形成一个或多个掩模开口。 非晶隔离层在图案化期间将电子反向散射的电子与光致抗蚀剂层隔离，从而减轻CD和由背散射电子引起的重叠误差。

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