公开(公告)号：US20220345116A1

公开(公告)日：2022-10-27

申请号：US17861205

申请日：2022-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Jerry Chang-Jui KAO ,  Tzu-Ying LIN

IPC: H03K3/037 ,  G01R31/3187 ,  H01L27/02 ,  H01L29/66 ,  H01L29/417

Abstract: An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.

公开(公告)号：US20200328210A1

公开(公告)日：2020-10-15

申请号：US16806978

申请日：2020-03-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Po-Chun WANG ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/092 ,  H01L23/538 ,  H01L29/06

Abstract: An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.

公开(公告)号：US20200285792A1

公开(公告)日：2020-09-10

申请号：US16881706

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei LEI ,  Chi-Lin LIU ,  Hui-Zhong ZHUANG ,  Zhe-Wei JIANG ,  Chi-Yu LU ,  Yi-Hsin KO

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20180165399A1

公开(公告)日：2018-06-14

申请号：US15660130

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Chan YANG ,  Hui-Zhong ZHUANG ,  Ting-Wei CHIANG ,  Yun-Xiang LIN ,  Tien-Yu KUO ,  Shu-Yi YING

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/12 ,  H01L21/77 ,  Y02P90/265

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

公开(公告)号：US20180006009A1

公开(公告)日：2018-01-04

申请号：US15201200

申请日：2016-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Pin-Dai SUE ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/12 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L2027/11875

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US20150031194A1

公开(公告)日：2015-01-29

申请号：US14511932

申请日：2014-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hang YANG ,  Chun-Fu CHEN ,  Pin-Dai SUE ,  Hui-Zhong ZHUANG

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/60 ,  H01L21/283

CPC classification number: H01L21/28008 ,  H01L21/283 ,  H01L21/76895 ,  H01L23/60 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

Abstract translation: 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。