公开(公告)号：US20210184110A1

公开(公告)日：2021-06-17

申请号：US17184997

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tien-Wei Chiang ,  Wen-Chun You

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

公开(公告)号：US20210134668A1

公开(公告)日：2021-05-06

申请号：US17007260

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huang Huang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen

IPC: H01L21/768 ,  G11C5/06 ,  G11C11/16 ,  H01L21/3213

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.

公开(公告)号：US10727274B2

公开(公告)日：2020-07-28

申请号：US16412714

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/10 ,  H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L43/12 ,  H01F41/32

Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.

公开(公告)号：US09666790B2

公开(公告)日：2017-05-30

申请号：US14801988

申请日：2015-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tien-Wei Chiang ,  Wen-Chun You

IPC: H01L29/82 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

公开(公告)号：US12279437B2

公开(公告)日：2025-04-15

申请号：US18362817

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

公开(公告)号：US12256647B2

公开(公告)日：2025-03-18

申请号：US18311191

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Yao Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang

IPC: H10N50/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

公开(公告)号：US11800724B2

公开(公告)日：2023-10-24

申请号：US17562949

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

公开(公告)号：US11785862B2

公开(公告)日：2023-10-10

申请号：US17319590

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Heng Liao ,  Harry-Hak-Lay Chuang ,  Chang-Jen Hsieh ,  Hung Cho Wang

IPC: H01L43/02 ,  H10N50/80 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N70/063 ,  H10N70/826

Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.

公开(公告)号：US20230189657A1

公开(公告)日：2023-06-15

申请号：US17725146

申请日：2022-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-HakLay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang ,  Hung-Yu Chang ,  Keng-Ming Kuo

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: Improved methods of patterning magnetic tunnel junctions (MTJs) for magnetoresistive random-access memory (MRAM) and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a bottom electrode layer over a semiconductor substrate; depositing an MTJ film stack over the bottom electrode layer; depositing a top electrode layer over the MTJ film stack; patterning the top electrode layer; performing a first etch process to pattern the MTJ film stack; performing a first trim process on the MTJ film stack; after performing the first trim process, depositing a first spacer layer over the MTJ film stack; and after depositing the first spacer layer, performing a second etch process to pattern the first spacer layer, the MTJ film stack, and the bottom electrode layer to form an MRAM cell.

公开(公告)号：US11322543B2

公开(公告)日：2022-05-03

申请号：US16884353

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.