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    Semiconductor Device and Method
    32.
    发明申请
    Semiconductor Device and Method 有权

    公开(公告)号：US20220375793A1

    公开(公告)日：2022-11-24

    申请号：US17874741

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih

    IPC: H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

    Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

    Integrated Circuit Package and Method
    34.
    发明申请
    Integrated Circuit Package and Method 有权

    公开(公告)号：US20220359326A1

    公开(公告)日：2022-11-10

    申请号：US17872916

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen ,  Hsien-Wei Chen ,  Tzuan-Horng Liu

    IPC: H01L23/31 ,  H01L23/538 ,  H01L23/48 ,  H01L23/522

    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

    Integrated Circuit Package and Method of Forming Same
    35.
    发明申请
    Integrated Circuit Package and Method of Forming Same 有权

    公开(公告)号：US20220319941A1

    公开(公告)日：2022-10-06

    申请号：US17808632

    申请日：2022-06-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chen-Hua Yu

    IPC: H01L23/28 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00

    Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.

    Integrated Circuit Package and Method of Forming Thereof
    36.
    发明申请
    Integrated Circuit Package and Method of Forming Thereof 有权

    公开(公告)号：US20220301890A1

    公开(公告)日：2022-09-22

    申请号：US17328001

    申请日：2021-05-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

    Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

    Package structure and method of fabricating the same
    40.
    发明授权
    Package structure and method of fabricating the same 有权

    公开(公告)号：US11417587B2

    公开(公告)日：2022-08-16

    申请号：US16856044

    申请日：2020-04-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

    IPC: H01L23/48 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.

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