公开(公告)号：US11901218B2

公开(公告)日：2024-02-13

申请号：US17715261

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US11854800B2

公开(公告)日：2023-12-26

申请号：US17329477

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/02321 ,  H01L21/02271 ,  H01L21/02345 ,  H01L21/02373 ,  H01L21/76224 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US11502121B2

公开(公告)日：2022-11-15

申请号：US16909024

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

公开(公告)号：US20220336644A1

公开(公告)日：2022-10-20

申请号：US17809976

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chien-Tai Chan ,  Liang-Yin Chen ,  Yee-Chia Yeo ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US20220278097A1

公开(公告)日：2022-09-01

申请号：US17186293

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20210225813A1

公开(公告)日：2021-07-22

申请号：US17223292

申请日：2021-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Meng-Hsun Wan ,  Dun-Nian Yaung

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

公开(公告)号：US10163951B2

公开(公告)日：2018-12-25

申请号：US15170200

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device has an isolation well region surrounding a photodetector arranged within a substrate at a first depth. A gate stack is arranged over the isolation well region along a first surface of the substrate. The gate stack defines an edge. A doped isolation feature is arranged within the substrate at a second depth between the isolation well region and the gate stack. The gate stack is vertically over an active area. The doped isolation feature extends from the edge of the gate stack to under the gate stack.

公开(公告)号：US20160276382A1

公开(公告)日：2016-09-22

申请号：US15170200

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14689

Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device has an isolation well region surrounding a photodetector arranged within a substrate at a first depth. A gate stack is arranged over the isolation well region along a first surface of the substrate. The gate stack defines an edge. A doped isolation feature is arranged within the substrate at a second depth between the isolation well region and the gate stack. The gate stack is vertically over an active area. The doped isolation feature extends from the edge of the gate stack to under the gate stack.

Abstract translation: 在一些实施例中，本公开涉及一种图像传感器装置。 图像传感器装置具有围绕设置在第一深度的衬底内的光电检测器的隔离阱区域。 栅极堆叠沿着衬底的第一表面布置在隔离阱区域的上方。 门堆栈定义一个边。 在隔离阱区域和栅极堆叠之间的第二深度处，在衬底内布置掺杂隔离特征。 栅极堆栈垂直于有效区域。 掺杂隔离特征从栅极堆叠的边缘延伸到栅极堆叠下方。

公开(公告)号：US12206012B2

公开(公告)日：2025-01-21

申请号：US17333592

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

公开(公告)号：US20240405096A1

公开(公告)日：2024-12-05

申请号：US18328207

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Szu-Ying Chen ,  Yung-Chung Chen ,  Sen-Hong Syue ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A method includes etching a first trench in a semiconductor substrate to form a first fin and a second fin, and forming a shallow trench isolation (STI) region in the first trench, where forming the STI region includes depositing a first dielectric layer over top surfaces of the first fin and the second fin, and on sidewalls and a bottom surface of the first trench, the first dielectric layer including carbon, depositing a second dielectric layer over the first dielectric layer, and in the first trench, where the second dielectric layer fills the first trench, and performing an anneal process, where the anneal process releases carbon from the first dielectric layer into the second dielectric layer.