公开(公告)号：US11410953B2

公开(公告)日：2022-08-09

申请号：US16983282

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ho ,  Yi-Wen Wu ,  Chien Ling Hwang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC: H01L21/56 ,  H01L27/112 ,  H01L23/31 ,  H01L21/48 ,  H01L21/3105 ,  H01L25/065 ,  H01L27/02 ,  H01L23/00

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

公开(公告)号：US11302650B2

公开(公告)日：2022-04-12

申请号：US16921907

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Shin-Puu Jeng ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

公开(公告)号：US11114313B2

公开(公告)日：2021-09-07

申请号：US16413915

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wen Liu ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Shin-Puu Jeng

IPC: H01L21/56 ,  B29C45/34 ,  B29C45/27 ,  B29L31/34

Abstract: A mold chase is provided, including a lower mold support and an upper mold support which are configured to be pressed together to form a mold cavity therebetween for receiving a wafer level substrate. The mold chase also includes multiple gates and at least one vent disposed along the periphery of the mold cavity. The gates are configured to allow a mold material to be injected into the mold cavity, and the vents are configured to release gas from the mold cavity. The distance between one of the gates and the closest vent is less than the diameter of the mold cavity.

公开(公告)号：US10930586B2

公开(公告)日：2021-02-23

申请号：US16416278

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/12 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/538 ,  H01L25/10

Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias. The conductive terminals are disposed over the second surface of the insulating encapsulation. The barrier layers respectively are disposed between the conductive through vias and the conductive terminals.

公开(公告)号：US20200328153A1

公开(公告)日：2020-10-15

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.