公开(公告)号：US20230369049A1

公开(公告)日：2023-11-16

申请号：US18350583

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/31058 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/0273

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US10319695B2

公开(公告)日：2019-06-11

申请号：US15715659

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.

公开(公告)号：US20180301430A1

公开(公告)日：2018-10-18

申请号：US15489954

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Hung Kuo ,  Chin-Yu Ku ,  Yuh-Sen Chang ,  Hon-Lin Huang ,  Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji LII

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13082 ,  H01L2224/1403

Abstract: A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.

公开(公告)号：US11742204B2

公开(公告)日：2023-08-29

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US11594484B2

公开(公告)日：2023-02-28

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US11177228B2

公开(公告)日：2021-11-16

申请号：US16436795

申请日：2019-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

公开(公告)号：US20210028266A1

公开(公告)日：2021-01-28

申请号：US16866519

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yu Wu ,  Mirng-Ji Lii ,  Shang-Yun Tu ,  Ching-Hui Chen

IPC: H01L27/32 ,  H01L51/56

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

公开(公告)号：US20200328153A1

公开(公告)日：2020-10-15

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US10276528B2

公开(公告)日：2019-04-30

申请号：US15652251

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US10163842B2

公开(公告)日：2018-12-25

申请号：US15489954

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Hung Kuo ,  Chin-Yu Ku ,  Yuh-Sen Chang ,  Hon-Lin Huang ,  Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L33/50 ,  H01L23/00

Abstract: A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.