公开(公告)号：US20180174656A1

公开(公告)日：2018-06-21

申请号：US15635887

申请日：2017-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der CHIH ,  Hung-Chang YU ,  Ku-Feng LIN

IPC: G11C16/28 ,  G11C16/08

CPC classification number: G11C16/28 ,  G11C7/04 ,  G11C16/08 ,  G11C16/32 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.

公开(公告)号：US20180166131A1

公开(公告)日：2018-06-14

申请号：US15619084

申请日：2017-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang CHEN ,  Shao-Yu CHOU ,  Chun-Hao CHANG ,  Min-Shin WU ,  Yu-Der CHIH

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/409 ,  G11C11/413 ,  G11C11/418

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

公开(公告)号：US20180033484A1

公开(公告)日：2018-02-01

申请号：US15730398

申请日：2017-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Cheng CHOU ,  Yu-Der CHIH ,  Wen-Ting CHU

IPC: G11C13/00 ,  H01L27/24 ,  H01L23/522 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79 ,  H01L23/522 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1616

Abstract: A memory architecture includes: a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; and a second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter, wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances. The first and second variable resistance dielectric layers are formed using a single process recipe. The first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.

公开(公告)号：US20170125071A1

公开(公告)日：2017-05-04

申请号：US14929076

申请日：2015-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Fu LEE ,  Yu-Der CHIH ,  Hon-Jarn LIN ,  Yi-Chun SHIH

IPC: G11C7/06 ,  G11C7/22

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/22 ,  G11C11/161 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/063

Abstract: A device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when a first reference switch the reference switches is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when a second reference switch of the reference switches is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.