中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.017 seconds)

    COOLING SYSTEM FOR 3D IC
    2.
    发明申请
    COOLING SYSTEM FOR 3D IC 有权
    3D IC冷却系统

    公开(公告)号：US20150059362A1

    公开(公告)日：2015-03-05

    申请号：US14013125

    申请日：2013-08-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Cheng CHOU ,  Po-Hao LEE ,  Jonathan Tehan CHEN

    IPC: F25B21/02

    CPC classification number: H01L25/0657 ,  F25B21/02 ,  F25B2321/0212 ,  H01L23/38 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.

    Abstract translation: 使用至少一个热电冷却器来冷却三维集成电路（3D IC）的系统和方法，其通过多个导电柱连接到3D IC。 在一些实施例中，控制器控制对热电冷却器的供电，并且温度监视器向控制器提供温度输入。 在一些实施例中，控制器通过循环到热电冷却器的功率将3D IC的温度保持在预定范围内。

    METHOD AND APPARATUS FOR ADAPTIVE TIMING WRITE CONTROL IN A MEMORY
    3.
    发明申请
    METHOD AND APPARATUS FOR ADAPTIVE TIMING WRITE CONTROL IN A MEMORY 有权
    一种存储器中自适应时序写入控制的方法和装置

    公开(公告)号：US20140219002A1

    公开(公告)日：2014-08-07

    申请号：US13761545

    申请日：2013-02-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： PoHao LEE ,  Chung-Cheng CHOU

    IPC: G11C11/16 ,  G11C13/00

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2213/79

    Abstract: A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an MRAM cell or an RRAM cell. The resistive element is configured to have a first resistance in a first state of the memory cell and a second resistance in a second state of the memory cell. A source line, which is selectively coupled to the memory cell by an access transistor, is set to a second voltage level. A word line signal is asserted to apply a first bias voltage across the resistive element. The applied first bias voltage initiates a write operation at the memory cell. The word line signal is deasserted after a variable time duration based on a detection, during the write operation, of a current through the resistive element.

    Abstract translation: 耦合到存储器单元的电阻元件的位线被设置为第一电压电平。 存储器单元可以是MRAM单元或RRAM单元。 电阻元件被配置为在存储单元的第一状态下具有第一电阻，并且在存储单元的第二状态下具有第二电阻。 通过存取晶体管选择性地耦合到存储单元的源极线被设置为第二电压电平。 字线信号被断言以在电阻元件上施加第一偏置电压。 所施加的第一偏置电压在存储器单元处启动写入操作。 基于在写入操作期间通过电阻元件的电流的检测，字线信号在可变持续时间后被断言。

    RESISTIVE RANDOM ACCESS MEMORY DEVICE
    5.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权

    公开(公告)号：US20210280245A1

    公开(公告)日：2021-09-09

    申请号：US17330248

    申请日：2021-05-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chung-Cheng CHOU ,  Wen-Ting CHU

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

    METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT
    8.
    发明申请
    METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT 审中-公开
    用于读取辅助以补偿弱位的方法和装置

    公开(公告)号：US20150131394A1

    公开(公告)日：2015-05-14

    申请号：US14603393

    申请日：2015-01-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

    Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

    Abstract translation: 记忆辅助装置包括检测电路和补偿电路。 检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。 如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

    RESISTIVE MEMORY DEVICE WITH TRIMMABLE DRIVER AND SINKER AND METHOD OF OPERATIONS THEREOF
    9.
    发明申请
    RESISTIVE MEMORY DEVICE WITH TRIMMABLE DRIVER AND SINKER AND METHOD OF OPERATIONS THEREOF 审中-公开

    公开(公告)号：US20200350010A1

    公开(公告)日：2020-11-05

    申请号：US16932736

    申请日：2020-07-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Cheng CHOU

    IPC: G11C13/00 ,  G11C8/00 ,  G11C11/16

    Abstract: A device is disclosed. The device includes a first memory cell, a second memory cell, a first pair of a driver and a sinker, and a second pair of a driver and a sinker. The first memory cell is coupled between the first pair of the driver and the sinker through a first line and a second line. The second memory cell is coupled between the second pair of the driver and the sinker through a third line and a fourth line. The first pair of the driver and the sinker are configured to be controlled to have resistances depending on a row location of the first memory cell in a memory column.

Patent Agency Ranking