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公开(公告)号：US20220102428A1
公开(公告)日：2022-03-31
申请号：US17032155
申请日：2020-09-25
发明人： Chieh-Fei CHIU , Wen-Ting CHU , Yong-Shiuan TSAIR , Yu-Wen LIAO , Chih-Yang CHANG , Chin-Chieh YANG
IPC分类号： H01L27/24 , H01L27/1159 , H01L27/11592 , H01L27/22 , H01L43/02 , H01L43/12 , H01L45/00
摘要： A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
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公开(公告)号：US20210082928A1
公开(公告)日：2021-03-18
申请号：US16569487
申请日：2019-09-12
发明人： Tzu-Yu CHEN , Sheng-Hung SHIH , Kuo-Chi TU , Wen-Ting CHU
IPC分类号： H01L27/1159 , H01L23/522
摘要： A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.
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公开(公告)号：US20220223651A1
公开(公告)日：2022-07-14
申请号：US17709845
申请日：2022-03-31
发明人： Chieh-Fei CHIU , Yong-Shiuan TSAIR , Wen-Ting CHU , Yu-Wen LIAO , Chin-Yu MEI , Po-Hao TSENG
摘要： A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.
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公开(公告)号：US20190103493A1
公开(公告)日：2019-04-04
申请号：US16207081
申请日：2018-11-30
发明人： Kuo-Chi TU , Jen-Sheng YANG , Sheng-Hung SHIH , Tong-Chern ONG , Wen-Ting CHU
IPC分类号： H01L29/78 , H01L29/51 , H01L29/66 , G11C11/22 , H01L27/1159 , H01L27/11592
摘要： A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US20150371721A1
公开(公告)日：2015-12-24
申请号：US14842815
申请日：2015-09-01
发明人： Wen-Ting CHU , Yue-Der CHIH
CPC分类号： G11C29/76 , G11C13/0002 , G11C13/0021 , G11C13/0023 , G11C13/0069 , G11C29/027 , G11C2029/4402
摘要： A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.
摘要翻译： 本文公开了一种设备，其包括存储区域和基于电阻读取存取存储器（基于RRAM或基于ReRAM的）非易失性存储阵列。 存储区域包括第一存储阵列和第二存储阵列。 第一存储阵列包括多个第一存储单元。 第二存储阵列包括多个第二存储单元。 第二存储单元被配置为代替第一存储单元。 基于RRAM的非易失性存储阵列被配置为记录第一存储单元和第二存储单元之间的至少一个对应关系。
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公开(公告)号：US20210408373A1
公开(公告)日：2021-12-30
申请号：US16912341
申请日：2020-06-25
发明人： Hsia-Wei CHEN , Chih-Hung PAN , Chih-Hsiang CHANG , Yu-Wen LIAO , Wen-Ting CHU
IPC分类号： H01L45/00
摘要： A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.
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公开(公告)号：US20210280245A1
公开(公告)日：2021-09-09
申请号：US17330248
申请日：2021-05-25
发明人： Yu-Der CHIH , Chung-Cheng CHOU , Wen-Ting CHU
摘要： A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
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公开(公告)号：US20180151746A1
公开(公告)日：2018-05-31
申请号：US15640127
申请日：2017-06-30
发明人： Kuo-Chi Tu , Jen-Sheng YANG , Sheng-Hung SHIH , Tong-Chern ONG , Wen-Ting CHU
IPC分类号： H01L29/78 , H01L27/1159 , H01L27/11592 , H01L29/51 , H01L29/66 , G11C11/22
CPC分类号： H01L29/78391 , G11C11/223 , G11C11/2257 , G11C11/2273 , H01L27/1159 , H01L27/11592 , H01L29/513 , H01L29/516 , H01L29/66545 , H01L29/6684
摘要： A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US20180033484A1
公开(公告)日：2018-02-01
申请号：US15730398
申请日：2017-10-11
发明人： Chung-Cheng CHOU , Yu-Der CHIH , Wen-Ting CHU
IPC分类号： G11C13/00 , H01L27/24 , H01L23/522 , H01L45/00
CPC分类号： G11C13/0069 , G11C11/005 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/0033 , G11C13/0035 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/79 , H01L23/522 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1616
摘要： A memory architecture includes: a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; and a second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter, wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances. The first and second variable resistance dielectric layers are formed using a single process recipe. The first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.
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公开(公告)号：US20240153559A1
公开(公告)日：2024-05-09
申请号：US18417729
申请日：2024-01-19
发明人： Yu-Der CHIH , Chung-Cheng CHOU , Wen-Ting CHU
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , H10B63/30 , H10B63/80 , H10B63/84 , H10N70/253 , H10N70/841 , G11C13/0007 , G11C2013/0045 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H10N70/20 , H10N70/826 , H10N70/8833
摘要： A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
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