公开(公告)号：US20180151579A1

公开(公告)日：2018-05-31

申请号：US15694098

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US09768220B2

公开(公告)日：2017-09-19

申请号：US14253025

申请日：2014-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/14638 ,  H01L21/76232 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L27/14692 ,  H01L29/0649

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.

公开(公告)号：US09570454B2

公开(公告)日：2017-02-14

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20160379987A1

公开(公告)日：2016-12-29

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20150279849A1

公开(公告)日：2015-10-01

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。