公开(公告)号：US20230119732A1

公开(公告)日：2023-04-20

申请号：US18068110

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Shen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

公开(公告)号：US11552103B2

公开(公告)日：2023-01-10

申请号：US17018139

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Bo-Feng Young ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L27/11597 ,  G11C7/18 ,  G11C11/14 ,  H01L27/11587

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

公开(公告)号：US11545500B2

公开(公告)日：2023-01-03

申请号：US17157489

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  G11C7/18

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

公开(公告)号：US20220416085A1

公开(公告)日：2022-12-29

申请号：US17884285

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L29/24 ,  H01L27/11597 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H01L27/1159

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US11527609B2

公开(公告)日：2022-12-13

申请号：US16916466

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L27/118 ,  H01L21/8238 ,  H01L27/092

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.

公开(公告)号：US20220384484A1

公开(公告)日：2022-12-01

申请号：US17884348

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L27/11597 ,  H01L29/06 ,  H01L27/11587

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

公开(公告)号：US20220367663A1

公开(公告)日：2022-11-17

申请号：US17814998

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/417

Abstract: The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to the gate electrode or the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.

公开(公告)号：US20220367344A1

公开(公告)日：2022-11-17

申请号：US17871029

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

Abstract: A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.

公开(公告)号：US11502128B2

公开(公告)日：2022-11-15

申请号：US17123925

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L23/522 ,  G11C7/18 ,  G11C8/14

Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

公开(公告)号：US11501812B2

公开(公告)日：2022-11-15

申请号：US17099094

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/51

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.