公开(公告)号：US20220328395A1

公开(公告)日：2022-10-13

申请号：US17852961

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

公开(公告)号：US11156772B2

公开(公告)日：2021-10-26

申请号：US16995145

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Pin-Tso Lin ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  G02B6/122

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

公开(公告)号：US20210305146A1

公开(公告)日：2021-09-30

申请号：US16919298

申请日：2020-07-02

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

公开(公告)号：US20210098408A1

公开(公告)日：2021-04-01

申请号：US17121353

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20210018678A1

公开(公告)日：2021-01-21

申请号：US16995145

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Pin-Tso Lin ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  G02B6/122

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

公开(公告)号：US20250069985A1

公开(公告)日：2025-02-27

申请号：US18543819

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Jian-Wei Hong

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.

公开(公告)号：US20240385398A1

公开(公告)日：2024-11-21

申请号：US18787083

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/48

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US20240258261A1

公开(公告)日：2024-08-01

申请号：US18629641

申请日：2024-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US12027455B2

公开(公告)日：2024-07-02

申请号：US17852961

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49861 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/5384

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

公开(公告)号：US11978714B2

公开(公告)日：2024-05-07

申请号：US18068064

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.