公开(公告)号：US20240136220A1

公开(公告)日：2024-04-25

申请号：US18401955

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US11923432B2

公开(公告)日：2024-03-05

申请号：US18149224

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US20230386832A1

公开(公告)日：2023-11-30

申请号：US18365517

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/02321 ,  H01L29/66795 ,  H01L29/66545 ,  H01L21/02271 ,  H01L21/823481 ,  H01L21/76895 ,  H01L21/76883 ,  H01L21/76224 ,  H01L21/02345 ,  H01L21/02373

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US20230144899A1

公开(公告)日：2023-05-11

申请号：US18149224

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L29/42392 ,  H01L29/6653 ,  H01L21/823412 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US20220230910A1

公开(公告)日：2022-07-21

申请号：US17715261

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US11302567B2

公开(公告)日：2022-04-12

申请号：US16917159

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US20210280414A1

公开(公告)日：2021-09-09

申请号：US17329477

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US09929268B2

公开(公告)日：2018-03-27

申请号：US15099607

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chii-Ming Wu ,  Ru-Shang Hsiao ,  Hung Pin Chen ,  Sen-Hong Syue ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method of fabricating a FinFET includes at last the following steps. A direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.

公开(公告)号：US20170301793A1

公开(公告)日：2017-10-19

申请号：US15099607

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chii-Ming Wu ,  Ru-Shang Hsiao ,  Hung Pin Chen ,  Sen-Hong Syue ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method of fabricating a FinFET includes at last the following steps. A direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.