公开(公告)号：US20200091142A1

公开(公告)日：2020-03-19

申请号：US16133795

申请日：2018-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Shi-Ning JU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308 ,  H01L21/8234

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

公开(公告)号：US20190164970A1

公开(公告)日：2019-05-30

申请号：US16059827

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167 ,  H01L29/161

Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.

公开(公告)号：US20190035912A1

公开(公告)日：2019-01-31

申请号：US15663089

申请日：2017-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.

公开(公告)号：US20190006486A1

公开(公告)日：2019-01-03

申请号：US15635337

申请日：2017-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

公开(公告)号：US20250142954A1

公开(公告)日：2025-05-01

申请号：US19007076

申请日：2024-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H10D84/85 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H10D30/01 ,  H10D30/62 ,  H10D30/69 ,  H10D62/10 ,  H10D62/13 ,  H10D62/822 ,  H10D62/832 ,  H10D62/834 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.

公开(公告)号：US20240387538A1

公开(公告)日：2024-11-21

申请号：US18786324

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work function layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work function layer fully fills spaces between the second channel nanostructures.

公开(公告)号：US20240379367A1

公开(公告)日：2024-11-14

申请号：US18784624

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.

公开(公告)号：US20230387236A1

公开(公告)日：2023-11-30

申请号：US18446151

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin CHEN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/78696 ,  H01L29/66545

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

公开(公告)号：US20230187545A1

公开(公告)日：2023-06-15

申请号：US18165102

申请日：2023-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang CHUANG ,  Ching-Wei TSAI ,  Wang-Chun HUANG ,  Kuan-Lun CHENG

IPC: H01L29/775 ,  H01L23/522 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L29/775 ,  H01L23/5226 ,  H01L29/0669 ,  H01L21/02603 ,  H01L29/66439 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/0257

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

公开(公告)号：US20220352164A1

公开(公告)日：2022-11-03

申请号：US17861565

申请日：2022-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.