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    Layout of a MOS array edge with density gradient smoothing
    31.
    发明授权
    Layout of a MOS array edge with density gradient smoothing 有权
    具有密度梯度平滑的MOS阵列边缘的布局

    公开(公告)号：US08759163B2

    公开(公告)日：2014-06-24

    申请号：US13744532

    申请日：2013-01-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Wen-Shen Chou ,  Jui-Cheng Huang

    IPC: H01L21/82 ,  H01L29/00 ,  H01L29/06

    CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/04

    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

    Abstract translation: 公开了一种多步密度梯度平滑布局样式，其中多个单位单元被布置成具有特征密度的阵列。 阵列的一个或多个边缘由第一边缘子阵列界定，该第一边缘子阵列的特征密度小于阵列的特征密度。 第一边缘子阵列由第二边缘子阵列邻接，第二边缘子阵列的特征密度小于第一边缘子阵列的特征密度，并且接近背景电路的特征密度。

    Area optimized series gate layout structure for FINFET array
    32.
    发明授权
    Area optimized series gate layout structure for FINFET array 有权
    FINFET阵列的面积优化系列门极布局结构

    公开(公告)号：US08719759B1

    公开(公告)日：2014-05-06

    申请号：US13778403

    申请日：2013-02-27

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Wen-Shen Chou ,  Chin-Hua Wen ,  Yung-Chow Peng ,  Chih-Chiang Chang

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.

    Abstract translation: 本公开内容涉及一种优化FinFET器件的串联栅极布局结构的面积的方法。 该方法分析集成芯片（IC）布局以确定沿着第一方向的第一栅极材料密度，并且基于第一栅极材料密度沿着第二方向单独地确定第二栅极材料密度。 基于FinFET器件的第二栅极材料密度和一个或多个器件性能参数来选择用于具有沿着第二方向的栅极长度的FinFET（场效应晶体管）器件的多个串联栅极级。 通过分析栅极材料在不同方向上的密度，可以增加FinFET的栅极的有效长度，而不增加晶体管阵列的尺寸。

    3D thermal detection circuits and methods
    34.
    发明授权
    3D thermal detection circuits and methods 有权

    公开(公告)号：US11692880B2

    公开(公告)日：2023-07-04

    申请号：US17140722

    申请日：2021-01-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Szu-Lin Liu ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: G01K7/21 ,  G01K7/20

    CPC classification number: G01K7/21 ,  G01K7/20

    Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

    CIRCUITS AND METHODS FOR REDUCING KICKBACK NOISE IN A COMPARATOR
    36.
    发明申请
    CIRCUITS AND METHODS FOR REDUCING KICKBACK NOISE IN A COMPARATOR 审中-公开

    公开(公告)号：US20200106422A1

    公开(公告)日：2020-04-02

    申请号：US16457459

    申请日：2019-06-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: H03K3/013 ,  H03K3/023

    Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

    Low gds measurement methodology for MOS
    39.
    发明授权
    Low gds measurement methodology for MOS 有权
    MOS的低gds测量方法

    公开(公告)号：US09429607B2

    公开(公告)日：2016-08-30

    申请号：US14107140

    申请日：2013-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Po-Zeng Kang

    IPC: G01R27/08 ,  G01R31/26 ,  G01N27/02

    CPC classification number: G01R27/08 ,  G01N27/025 ,  G01R31/2621

    Abstract: A dummy MOSFET is connected in series with a device under test to form cascode structure. The conductance of the low conductance MOSFET is derived from the measurements done on the cascode structure. An open loop gain stage is connected to the cascode structure in case the signal at the internal node of the cascode structure is extremely small to be measured directly and accurately. Impedance measurements can also be done on high impedance MOS devices without noise distortion with the help of the cascode arrangement.

    Abstract translation: 虚拟MOSFET与被测器件串联连接以形成共源共栅结构。 低导通MOSFET的电导来自于在共源共栅结构上进行的测量。 在共源共栅结构的内部节点处的信号非常小以直接和准确地测量的情况下，开环增益级连接到共源共栅结构。 借助于共源共栅布置，也可以在高阻抗MOS器件上实现阻抗测量，而无噪声失真。

    High speed communication interface with an adaptive swing driver to reduce power consumption
    40.
    发明授权
    High speed communication interface with an adaptive swing driver to reduce power consumption 有权
    高速通讯接口具有自适应摆动驱动器，以降低功耗

    公开(公告)号：US09099990B2

    公开(公告)日：2015-08-04

    申请号：US13792257

    申请日：2013-03-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC: H03K19/094 ,  H03K3/012 ,  H03K19/00 ,  H03K19/0185

    CPC classification number: H03K3/012 ,  H03K19/0013 ,  H03K19/018521

    Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

    Abstract translation: 具有自适应摆动驱动器的高速总线接口。 高速接口包括通过总线耦合的发射机和接收机。 发射机具有自适应摆幅驱动器和电压调节模块（VRM）。 自适应摆动驱动器包括后驱动器和预驱动器。 后驱动器通过内部逻辑电压电源（VDD）提供具有专用自适应电压电源（VDDQ）和过渡强调驱动能力的自适应摆幅输出。 前驱动器通过上拉和下拉信号路径向后驱动器提供过渡强调驱动能力。 电压调节模块被配置为向自适应摆动驱动器提供信号。 接收机包括一个比较器和一个误码率检测器。 比较器通过总线放大从发送器接收的自适应摆幅输出，而误码率检测器诊断从比较器接收的放大的自适应摆幅输出。

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