公开(公告)号：US11695007B2

公开(公告)日：2023-07-04

申请号：US17030122

申请日：2020-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsiang Wang ,  Szu-Lin Liu ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/687 ,  H01L23/64 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/642 ,  H01L27/0222 ,  H03K17/6872

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

公开(公告)号：US11308255B2

公开(公告)日：2022-04-19

申请号：US16886550

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367 ,  G06F30/3953 ,  G06F30/373 ,  G06F119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.

公开(公告)号：US10979065B1

公开(公告)日：2021-04-13

申请号：US16836923

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H03M1/46

Abstract: A signal processing circuit including a plurality of analog-to-digital conversion circuits, an in-memory computing device, and a control method thereof are provided. Each analog-to-digital conversion circuit includes a reset switch, a capacitor array circuit, a voltage comparator, and a successive approximation circuit. A first terminal of the reset switch receives a first reference voltage, and a second terminal of the reset switch receives an input voltage signal. The capacitor array circuit adjusts the input voltage signal according to a successive approximation control signal to generate an adjusted voltage. The voltage comparator compares the voltage levels of the adjusted voltage and a second reference voltage to generate a comparison signal. The successive approximation circuit generates a successive approximation control signal according to the comparison signal and generates an output digital signal corresponding to the input voltage signal. The capacitor array circuit maintains the input voltage signal during a non-reset stage.

公开(公告)号：US10883884B2

公开(公告)日：2021-01-05

申请号：US16378277

申请日：2019-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Lin Liu ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: G01K7/21 ,  G01K7/20

Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

公开(公告)号：US10692549B1

公开(公告)日：2020-06-23

申请号：US16572604

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chow Peng ,  Chin-Ho Chang ,  Jaw-Juinn Horng

IPC: H03M1/12 ,  G11C7/12 ,  G06F12/06 ,  H03M1/06 ,  H03M1/10 ,  H03M1/80 ,  G11C13/00

Abstract: A memory array structure that includes memory columns having first bit lines and second bit lines is introduced. Each of the memory columns includes a bit line pair, a pre-charge switch pair and a first switch pair. Output voltages from the first bit lines and the second bit lines are used to generated a first average voltage and a second average voltage, respectively. One of the first average voltage and the second average voltage is a lower average voltage and another one of the first average voltage and the second average voltage is a higher average voltage. The pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.

公开(公告)号：US10141934B2

公开(公告)日：2018-11-27

申请号：US15794331

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tao Yang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: H03K19/017 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.

公开(公告)号：US09379112B2

公开(公告)日：2016-06-28

申请号：US14192121

申请日：2014-02-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Ching-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H01L27/118 ,  H01L21/82 ,  H01L27/10 ,  G05F3/26 ,  H01L29/423 ,  H01L27/06 ,  H01L27/07

CPC classification number: G05F3/262 ,  G06F17/5072 ,  H01L27/0617 ,  H01L27/0705 ,  H01L27/10 ,  H01L29/42376

Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.

Abstract translation: 集成电路包括多个晶体管。 晶体管串联电连接并且其各自的栅极连接在一起。 晶体管被实现在晶体管阵列内。 晶体管电连接在第一参考端和第二参考端之间。 与第一参考端相邻的晶体管的非支配部分实现在晶体管阵列的角区。

公开(公告)号：US20150168468A1

公开(公告)日：2015-06-18

申请号：US14107140

申请日：2013-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chow Peng ,  Po-Zeng Kang

IPC: G01R27/08

CPC classification number: G01R27/08 ,  G01N27/025 ,  G01R31/2621

Abstract: A dummy MOSFET is connected in series with a device under test to form cascode structure. The conductance of the low conductance MOSFET is derived from the measurements done on the cascode structure. An open loop gain stage is connected to the cascode structure in case the signal at the internal node of the cascode structure is extremely small to be measured directly and accurately. Impedance measurements can also be done on high impedance MOS devices without noise distortion with the help of the cascode arrangement.

Abstract translation: 虚拟MOSFET与被测器件串联连接以形成共源共栅结构。 低导通MOSFET的电导来自于在共源共栅结构上进行的测量。 在共源共栅结构的内部节点处的信号非常小以直接和准确地测量的情况下，开环增益级连接到共源共栅结构。 借助于共源共栅布置，也可以在高阻抗MOS器件上实现阻抗测量，而无噪声失真。

公开(公告)号：US12249601B2

公开(公告)日：2025-03-11

申请号：US16942264

申请日：2020-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Zeng Kang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: H01L27/06 ,  G06F30/392 ,  G06F30/3953 ,  H01L23/522 ,  H01L27/02 ,  H03K19/0944

Abstract: An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.

公开(公告)号：US12073167B2

公开(公告)日：2024-08-27

申请号：US18163916

申请日：2023-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.