公开(公告)号：US20140218999A1

公开(公告)日：2014-08-07

申请号：US14124725

申请日：2011-06-10

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Akira Kotabe ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Akira Kotabe ,  Takashi Kobayashi

IPC分类号： G11C13/00

CPC分类号： G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.

摘要翻译： 为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。 也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线 在相应的捆绑的两条字线上垂直形成的电路分离。 这样的配置使得可以：在电线的捆扎部分（MLC）处形成更大的接触; 并降低适于小型化的存储器阵列中的接触电阻。

公开(公告)号：US08592789B2

公开(公告)日：2013-11-26

申请号：US13109985

申请日：2011-05-17

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472

摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

公开(公告)号：US20130141968A1

公开(公告)日：2013-06-06

申请号：US13814104

申请日：2011-08-26

申请人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

发明人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

IPC分类号： G11C13/00

CPC分类号： G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

摘要翻译： 本发明的目的是提高相变存储器的重写传输速率和可靠性。 为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件 彼此完全设置，之后，与数据模式对应的单元的一部分被重置。 或者，执行相反的操作。

公开(公告)号：US20130075684A1

公开(公告)日：2013-03-28

申请号：US13588112

申请日：2012-08-17

申请人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Hiroyuki Minemura

发明人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Hiroyuki Minemura

IPC分类号： H01L45/00 ,  B82Y99/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06

摘要： A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.

摘要翻译： 非易失性存储器件包括：沿衬底的主表面延伸的第一线; 提供在第一行之上的堆栈; 在堆叠之上形成第二线; 设置在所述第一和第二线相交的选择元件，所述选择元件适于在垂直于所述主表面的方向上传递电流; 沿着所述堆叠的侧表面设置的第二绝缘膜; 沿所述第二绝缘膜设置的沟道层; 沿着沟道层提供的粘合层; 以及沿着粘合层设置的可变电阻材料层，其中第一和第二线经由选择元件和沟道层电连接，通过沟道层和可变电阻材料层之间的粘合层的接触电阻低，并且 粘合层的电阻相对于沟道层的延伸方向高。

公开(公告)号：US20080261365A1

公开(公告)日：2008-10-23

申请号：US11865657

申请日：2007-10-01

申请人： Yoshitaka SASAGO ,  Takashi Kobayashi

发明人： Yoshitaka SASAGO ,  Takashi Kobayashi

IPC分类号： H01L21/8247

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328

摘要： A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate 3 of a memory cell with an inverse T-shape and the dimension of a part of the floating gate through the control gate 4 and the second insulator film 8 being smaller than the bottom part of the floating gate, the effects of a threshold voltage shift is reduced maintaining the adequate area of the gap between the floating gate 3 and the control gate 4, decreasing the opposing area of the gap of the floating gates 3 underneath the adjoining word lines WL, maintaining the capacity coupling ratio between the floating gate 3 and the control gate, and reducing the opposing area of the gap of the adjoining floating gates 3.

摘要翻译： 一种实现相邻浮栅之间的电容减小的技术和由非易失性半导体存储器件中相邻的存储单元之间的干扰引起的阈值电压偏移与90nm代之后的周期内的小型化的进步。 通过使具有逆T形的存储单元的浮置栅极3和通过控制栅极4和第二绝缘膜8的一部分浮动栅极的尺寸小于浮动栅极的底部的尺寸， 维持阈值电压偏移的维持维持浮动栅极3和控制栅极4之间的间隙的适当面积，减小相邻字线WL下面的浮动栅极3的间隙的相对面积，从而保持 浮动栅极3和控制栅极，并且减小邻接的浮动栅极3的间隙的相对面积。

公开(公告)号：US20050062096A1

公开(公告)日：2005-03-24

申请号：US10894311

申请日：2004-07-20

申请人： Yoshitaka Sasago ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Takashi Kobayashi

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device, in which an inversion layer formed over a semiconductor substrate is used as a data line, is achieved with its high integration and high performance. A memory cell is composed of a MOS transistor having a floating gate, a control gate constituting a word line, and a buried gate. The buried gate is buried in a groove formed in a self-alignment manner with respect to the floating gate. The buried gate and the control gate disposed over it are isolated from each other by a thick silicon oxide film on the groove and a second gate insulator film formed thereon. A source and drain of the memory cell are composed of an inversion layer (local data line) formed on a p type well disposed below the buried gate when a positive voltage is applied to the buried gate.

摘要翻译： 其中以半导体衬底形成的反型层用作数据线的非易失性半导体存储器件以高集成度和高​​性能实现。 存储单元由具有浮置栅极的MOS晶体管，构成字线的控制栅极和掩埋栅极构成。 掩埋栅埋在相对于浮动栅极以自对准方式形成的沟槽中。 埋置栅极和设置在其上的控制栅极通过沟槽上的厚氧化硅膜和形成在其上的第二栅极绝缘膜彼此隔离。 存储单元的源极和漏极由正电压施加到掩埋栅极上时，在埋置栅极下方的p型阱上形成的反型层（局部数据线）构成。

公开(公告)号：US10077485B2

公开(公告)日：2018-09-18

申请号：US14409549

申请日：2012-06-27

申请人： Takashi Kobayashi ,  Nobuyuki Nakamura ,  Yoshimasa Funakawa

发明人： Takashi Kobayashi ,  Nobuyuki Nakamura ,  Yoshimasa Funakawa

IPC分类号： C22C38/26 ,  C21D6/00 ,  C22C38/00 ,  C22C38/06 ,  C22C38/04 ,  C21D9/46 ,  C21D8/02 ,  C22C38/02 ,  C22C38/24 ,  C22C38/38 ,  C23C8/26

CPC分类号： C21D9/46 ,  C21D6/002 ,  C21D6/005 ,  C21D6/008 ,  C21D8/0226 ,  C21D8/0263 ,  C21D2211/005 ,  C21D2211/009 ,  C22C38/00 ,  C22C38/001 ,  C22C38/02 ,  C22C38/04 ,  C22C38/06 ,  C22C38/24 ,  C22C38/26 ,  C22C38/38 ,  C23C8/26

摘要： A steel sheet for soft-nitriding has a composition containing: C: 0.05% or more to 0.10% or less; Si: 0.5% or less; Mn: 0.7% or more to 1.5% or less; P: 0.05% or less; S: 0.01% or less; Al: 0.01% or more to 0.06% or less; Cr: 0.5% or more to 1.5% or less; V: 0.03% or more to 0.30% or less; and N: 0.005% or less, on a mass percent basis, wherein a ratio of amount of solute V to the V content (amount of solute V/V content) is more than 0.50, and balance comprises Fe and incidental impurities, and a complex-phase microstructure containing ferrite and pearlite.

公开(公告)号：US20150299830A1

公开(公告)日：2015-10-22

申请号：US14408662

申请日：2012-06-27

申请人： Takashi Kobayashi ,  Nobuyuki Nakamura ,  Tetsuya Mega

发明人： Takashi Kobayashi ,  Nobuyuki Nakamura ,  Tetsuya Mega

IPC分类号： C22C38/26 ,  C21D9/46 ,  C22C38/00 ,  C22C38/06 ,  C22C38/04 ,  C22C38/02 ,  C21D8/02 ,  C21D6/00

CPC分类号： C22C38/26 ,  C21D6/002 ,  C21D6/005 ,  C21D6/008 ,  C21D8/0263 ,  C21D9/46 ,  C21D2211/005 ,  C21D2211/009 ,  C22C38/00 ,  C22C38/001 ,  C22C38/002 ,  C22C38/02 ,  C22C38/04 ,  C22C38/06 ,  C23C8/32

摘要： A steel sheet for soft-nitriding has a composition containing: C: 0.05% or more to 0.10% or less; Si: 0.5% or less; Mn: 0.7% or more to 1.5% or less; P: 0.05% or less; S: 0.01% or less; Al: 0.01% or more to 0.06% or less; Cr: 0.5% or more to 1.5% or less; Nb: 0.005% or more to 0.025% or less; and N: 0.005% or less, on a mass percent basis, such that C and Nb satisfy 0.10≦Nb/C≦0.30 (where C and Nb are respective contents of the elements (by mass %)), wherein balance comprises Fe and incidental impurities, and a microstructure that is a complex-phase microstructure containing ferrite and pearlite, and the microstructure having a ratio of a microstructure other than the ferrite and the pearlite of 1% or less, and the microstructure having a ratio of polygonal ferrite in the ferrite of less than 50%.

摘要翻译： 软氮化钢板的组成为：C：0.05％以上且0.10％以下， Si：0.5％以下; Mn：0.7％以上至1.5％以下; P：0.05％以下; S：0.01％以下; Al：0.01％以上至0.06％以下; Cr：0.5％以上至1.5％以下; Nb：0.005％以上至0.025％以下; 和N：0.005％以下，C和Nb满足0.10＆nlE; Nb / C＆lt; NlE; 0.30（其中，C和Nb分别为元素含量（质量％）），其中余量包含Fe 和杂质，以及包含铁素体和珠光体的复相组织的显微组织以及具有1％以下的铁素体和珠光体以外的组织比的微结构，以及具有多边形铁素体 在铁素体中小于50％。

公开(公告)号：US08835872B2

公开(公告)日：2014-09-16

申请号：US13806989

申请日：2011-06-23

申请人： Takashi Kobayashi

发明人： Takashi Kobayashi

IPC分类号： H01J37/20

CPC分类号： H01J37/20 ,  H01J2237/20285 ,  H01J2237/20292 ,  H01J2237/2817 ,  H01L21/68

摘要： A sample stage device (10) is so configured as to calculate ideal position information xtg(i), tg(i) per predetermined period that is unaffected by drive conditions relating to gaps (25, 26), etc., and to determine, per predetermined cycle and in real time, deviations dx(i), dy(i) between real-time measured positions x(i), y(i) by position detectors comprising laser interferometers (33, 34), etc., and ideal position information xtg(i), tg(i). In addition, it calculates, based on deviations dx(i), dy(i) thus determined, such speed command values vx(i), vy(i) for motors (27, 28) that measured values x(i), y(i) would follow ideal position information xtg(i), tg(i), and performs stable and high-speed positioning control for a sample table (11) through feedback control that controls speed in real time. Thus, with respect to a sample stage device, it is possible to provide a stable and high-speed positioning control method for a sample table, which is capable of suppressing noise caused by thermal drift and vibration, without being affected by drive conditions, such as the initial states of gaps, etc.

摘要翻译： 样品台装置（10）被配置为计算不受与间隙（25,26）等有关的驱动条件的影响的每预定周期的理想位置信息xtg（i），tg（i） 并且实时地通过包括激光干涉仪（33,34）的位置检测器等实时测量位置x（i），y（i）之间的偏差dx（i），dy（i）和理想 位置信息xtg（i），tg（i）。 另外，根据如此确定的偏差dx（i），dy（i），计算出测量值x（i），y（i）的电动机（27,28）的速度指令值vx（i），vy （i）将遵循理想位置信息xtg（i），tg（i），并且通过实时控制速度的反馈控制对样本表（11）执行稳定和高速定位控制。 因此，对于样品台装置，可以提供一种用于样品台的稳定且高速的定位控制方法，其能够抑制由热漂移和振动引起的噪声，而不受驱动条件的影响，例如 作为差距的初始状态等

公开(公告)号：US08758253B2

公开(公告)日：2014-06-24

申请号：US12513858

申请日：2007-11-06

申请人： Shuzo Sano ,  Akifumi Sako ,  Takashi Kobayashi ,  Mikio Izumi

发明人： Shuzo Sano ,  Akifumi Sako ,  Takashi Kobayashi ,  Mikio Izumi

IPC分类号： A61B8/14 ,  A61B8/00

CPC分类号： A61B8/4281 ,  A61B8/4455 ,  A61B8/4483 ,  B06B1/0292 ,  H04R19/005

摘要： An ultrasonic probe is disclosed which includes a cMUT chip having a plurality of vibration elements whose electromechanical coupling coefficient or sensitivity is changed according to a bias voltage and transmitting and receiving ultrasonic waves, an acoustic lens arranged above the cMUT chip, and a backing layer arranged below the cMUT chip. An electric leakage preventing unit is provided at the ultrasonic wave transmission/reception surface side of the acoustic lens or between the acoustic lens and the cMUT chip. The electric leakage preventing unit can be, for example, an insulating layer such as a ground layer. Such a structure makes it is possible to provide an ultrasonic probe capable of preventing electric leakage from the ultrasonic probe to an object to be examined so as to improve the electric safety and an ultrasonic diagnostic apparatus using the probe.

摘要翻译： 公开了一种超声波探头，其包括具有多个振动元件的cMUT芯片，其中机电耦合系数或灵敏度根据偏置电压而变化，并且发送和接收超声波，布置在cMUT芯片上方的声透镜，以及布置在 在cMUT芯片之下。 在声透镜的超声波发送/接收表面侧或声透镜和cMUT芯片之间设置漏电防止单元。 防漏电单元可以是例如绝缘层，例如接地层。 通过这样的结构，能够提供能够防止从超声波探头向被检体的漏电以提高电气安全性的超声波探头以及使用该探针的超声波诊断装置。