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110 条记录 (耗时 0.047 秒)

    Semiconductor memory device
    31.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08759806B2

    公开(公告)日：2014-06-24

    申请号：US13182095

    申请日：2011-07-13

    申请人： Takeshi Yamaguchi ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

    发明人： Takeshi Yamaguchi ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

    IPC分类号： H01L29/02

    CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233

    摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

    摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

    SEMICONDUCTOR MEMORY DEVICE
    32.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20120012807A1

    公开(公告)日：2012-01-19

    申请号：US13182095

    申请日：2011-07-13

    申请人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

    发明人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

    IPC分类号： H01L45/00

    CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233

    摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

    摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

    Semiconductor device having first and second demodulation circuits for wireless communication
    33.
    发明授权
    Semiconductor device having first and second demodulation circuits for wireless communication 有权
    具有用于无线通信的第一和第二解调电路的半导体器件

    公开(公告)号：US08928400B2

    公开(公告)日：2015-01-06

    申请号：US13298897

    申请日：2011-11-17

    申请人： Takayuki Tsukamoto

    发明人： Takayuki Tsukamoto

    IPC分类号： H03D1/00 ,  H04L27/06 ,  H04B5/00

    CPC分类号： H04L27/06 ,  G06K7/0008 ,  H03D1/00 ,  H04B5/0031

    摘要： A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration.

    摘要翻译： 当NFC功能半导体器件以除R / W模式之外的模式工作时，器件通过使用与用于R / W模式的ASK信号接收电路不同的ASK信号接收电路来接收ASK信号。 在一对发送端子的一侧设置有用于100％ASK的ASK信号接收电路。 这种布置消除了在与一对接收终端耦合的10％ASK的ASK信号接收电路内提供的ESD的影响。 不需要根据ASK的类型来管理不同的阈值，并且可以通过较小的电路配置来支持不同的调制方案。

    Nonvolatile semiconductor memory device
    34.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08675388B2

    公开(公告)日：2014-03-18

    申请号：US13233679

    申请日：2011-09-15

    申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

    发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

    摘要： A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

    摘要翻译： 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

    Semiconductor integrated circuit and operating method thereof
    35.
    发明授权
    Semiconductor integrated circuit and operating method thereof 有权
    半导体集成电路及其操作方法

    公开(公告)号：US08374571B2

    公开(公告)日：2013-02-12

    申请号：US13279408

    申请日：2011-10-24

    申请人： Atsushi Motozawa ,  Takayuki Tsukamoto ,  Tatsuji Matsuura ,  Yuichi Okuda

    发明人： Atsushi Motozawa ,  Takayuki Tsukamoto ,  Tatsuji Matsuura ,  Yuichi Okuda

    IPC分类号： H04B1/28 ,  H04B1/06

    CPC分类号： H04B1/40 ,  H03H11/26 ,  H03K5/133

    摘要： An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

    摘要翻译： 集成电路配备有接收混频器和信号发生器。 多级延迟电路响应于接收载波信号而产生多个时钟脉冲。 相位检测单元检测特定时钟脉冲的电压电平和在特定时钟脉冲之前产生的预定数量的时钟脉冲的电压电平之间的差异，从而检测特定时钟脉冲的预定相位。 时钟生成单元的选择器从时钟脉冲信号输出分别具有多个相位的多个选择时钟脉冲信号。 第一信号合成逻辑电路对选择时钟脉冲执行逻辑运算，从而产生提供给接收混频器的本地信号。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    36.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20110103128A1

    公开(公告)日：2011-05-05

    申请号：US12882685

    申请日：2010-09-15

    申请人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

    发明人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

    摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

    摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    37.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20080238632A1

    公开(公告)日：2008-10-02

    申请号：US12057671

    申请日：2008-03-28

    申请人： Takefumi ENDO ,  Takayuki Tsukamoto

    发明人： Takefumi ENDO ,  Takayuki Tsukamoto

    IPC分类号： H04B7/00

    CPC分类号： H04B5/02 ,  H04B5/0031 ,  H04B5/0037

    摘要： In an IC tag, when a semiconductor integrated circuit device is activated, an operation control unit sets existence/nonexistence of a communication distance limitation for reducing a communication distance to a state management unit. If the communication distance limitation is not set, a switch unit is turned ON and a demodulated command is inputted from a command demodulation circuit to a command decode unit. If the communication distance limitation is set, a power intensity monitor unit judges whether the power of a rectification circuit is a predetermined arbitrary field intensity or more. If the power is smaller than the predetermined arbitrary field intensity, the switch unit is turned OFF and various commands demodulated by the command demodulation circuit are not inputted to the command decode unit. As a result, the semiconductor integrated circuit device does not operate.

    摘要翻译： 在IC标签中，当半导体集成电路器件被激活时，操作控制单元设置存在/不存在通信距离限制，以减少与状态管理单元的通信距离。 如果没有设定通信距离限制，则开关单元被接通，并且解调命令从命令解调电路输入到命令解码单元。 如果设置了通信距离限制，则功率强度监视单元判定整流电路的功率是否为预定的任意场强度以上。 如果功率小于预定的任意场强，则切换单元关闭，并且由命令解调电路解调的各种命令不被输入到命令解码单元。 结果，半导体集成电路器件不工作。

    Optical recording medium and optical recording-reproducing method
    38.
    发明授权
    Optical recording medium and optical recording-reproducing method 失效
    光记录介质和光记录再现方法

    公开(公告)号：US07245576B2

    公开(公告)日：2007-07-17

    申请号：US10758481

    申请日：2004-01-16

    申请人： Katsutaro Ichihara ,  Sumio Ashida ,  Keiichiro Yusu ,  Kenji Todori ,  Takayuki Tsukamoto

    发明人： Katsutaro Ichihara ,  Sumio Ashida ,  Keiichiro Yusu ,  Kenji Todori ,  Takayuki Tsukamoto

    IPC分类号： G11B7/24

    CPC分类号： B82Y10/00 ,  G11B7/00454 ,  G11B7/00456 ,  G11B7/005 ,  G11B7/242 ,  G11B7/243 ,  G11B7/253 ,  G11B7/257 ,  G11B7/261 ,  G11B7/268

    摘要： An optical recording medium includes an optical recording layer, a separating layer formed on a reproducing light incident side of the optical recording layer, and a phase-change reproducing layer formed on the reproducing light incident side of the separating layer, absorbance of which phase-change reproducing layer is changed depending on whether a state of the optical recording layer is a recording mark or a space. A transfer portion to which a state of the optical recording layer is transferred is formed in a portion having high absorbance of the phase-change reproducing layer by irradiation with reproducing light, while a portion of the phase-change reproducing layer other than the transfer portion is kept in a state optically differing from the transfer portion.

    摘要翻译： 光记录介质包括光记录层，形成在光记录层的再现光入射侧的分离层和形成在分离层的再现光入射侧的相变再现层， 改变再现层根据光学记录层的状态是记录标记还是空间而改变。 通过照射再生光，在相变再生层的吸光度高的部分形成转印了光记录层的状态的转印部分，而转印部分以外的相变再生层的一部分 保持在与转印部分光学不同的状态。