公开(公告)号：US20230393933A1

公开(公告)日：2023-12-07

申请号：US18453598

申请日：2023-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Son Hung Tran

IPC: G06F11/10 ,  H03M13/15 ,  G06F9/38 ,  G06F12/0879 ,  G06F9/30 ,  G06F9/46 ,  G06F9/448 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F13/16

CPC classification number: G06F11/106 ,  G06F11/1068 ,  H03M13/1575 ,  G06F9/3867 ,  G06F12/0879 ,  G06F9/30101 ,  G06F9/467 ,  G06F9/4498 ,  G06F9/4812 ,  G06F9/30047 ,  G06F9/52 ,  G06F12/0811 ,  G06F13/1668 ,  G06F2212/608

Abstract: A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

公开(公告)号：US11768733B2

公开(公告)日：2023-09-26

申请号：US17670582

申请日：2022-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Son Hung Tran

IPC: H03M13/27 ,  H04L27/34 ,  H04L1/00 ,  H03M13/25 ,  G06F11/10 ,  G06N3/045 ,  H03M13/15 ,  G06F9/38 ,  G06F12/0879 ,  G06F9/30 ,  G06F9/46 ,  G06F9/448 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F13/16

CPC classification number: G06F11/106 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/467 ,  G06F9/4812 ,  G06F9/52 ,  G06F11/1068 ,  G06F12/0811 ,  G06F12/0879 ,  G06F13/1668 ,  H03M13/1575 ,  G06F2212/608

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

公开(公告)号：US20230176975A1

公开(公告)日：2023-06-08

申请号：US18102804

申请日：2023-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung ONG

IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F9/3802 ,  G06F12/0811 ,  G06F2212/602

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

公开(公告)号：US11580024B2

公开(公告)日：2023-02-14

申请号：US17492776

申请日：2021-10-04

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US11494224B2

公开(公告)日：2022-11-08

申请号：US16882329

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

公开(公告)号：US11487616B2

公开(公告)日：2022-11-01

申请号：US16874516

申请日：2020-05-14

Applicant: Texas Instruments incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/08 ,  G06F9/38 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/126

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

公开(公告)号：US20220245069A1

公开(公告)日：2022-08-04

申请号：US17727921

申请日：2022-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

IPC: G06F12/1045 ,  G06F15/78

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

公开(公告)号：US20220156149A1

公开(公告)日：2022-05-19

申请号：US17588448

申请日：2022-01-31

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

公开(公告)号：US11314644B2

公开(公告)日：2022-04-26

申请号：US16882178

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson ,  Neelima Muralidharan

IPC: G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0831

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

公开(公告)号：US11307987B2

公开(公告)日：2022-04-19

申请号：US16882305

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria ,  Peter Michael Hippleheuser

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/0895 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F9/30 ,  G06F11/30 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.