公开(公告)号：US07998858B2

公开(公告)日：2011-08-16

申请号：US11588769

申请日：2006-10-27

申请人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

发明人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC分类号： H01L21/4763

CPC分类号： H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

摘要翻译： 本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂， 随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

公开(公告)号：US07316951B2

公开(公告)日：2008-01-08

申请号：US11191461

申请日：2005-07-28

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/8234

CPC分类号： H01L28/91 ,  H01L29/66181

摘要： The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side of the silicon substrate (1); depositing a layer (12) made of a metal oxide in the trench (5); carrying out a thermal treatment for selectively reducing the layer (12), a region of the layer (12) that lies below the insulation collar (10) above the silicon substrate (1) being reduced and being converted into a first capacitor electrode layer (15) made of a corresponding metal silicide, and a region of the layer (12) that lies above the insulation collar (10) not being reduced; selectively removing the non-reduced region of the layer (12) that lies above the insulation collar (10); providing a capacitor dielectric layer (18) in the trench (5) above the first capacitor electrode layer (15); and providing a second capacitor electrode layer (20) in the trench (5) above the capacitor dielectric layer (18).

摘要翻译： 本发明提供一种在硅衬底（1）中具有绝缘套环（10）的沟槽电容器的制造方法，其具有以下步骤：在硅衬底（1）中提供沟槽（5）; 在所述上沟槽区域中提供所述绝缘套环（10）直到所述硅衬底（1）的顶侧; 在沟槽（5）中沉积由金属氧化物制成的层（12）; 进行用于选择性地还原层（12）的热处理，位于硅衬底（1）上方的绝缘套环（10）下方的层（12）的区域被还原并被转换成第一电容器电极层 15），并且位于所述绝缘套环（10）上方的所述层（12）的不被还原的区域; 选择性地去除位于绝缘套环（10）上方的层（12）的非还原区域; 在第一电容器电极层（15）上方的沟槽（5）中提供电容器介电层（18）; 以及在电容器介电层（18）上方的沟槽（5）中提供第二电容器电极层（20）。

公开(公告)号：US07303970B2

公开(公告)日：2007-12-04

申请号：US11125654

申请日：2005-05-10

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/20

CPC分类号： H01L28/56 ,  H01L21/022 ,  H01L21/31604 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditioned, a dielectric layer (102) is deposited on the conditioned substrate (101) and a second electrode layer (104) is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer (102) deposited on the conditioned substrate (101) forms a dielectric mixed layer (105) with a reaction layer (103) deposited on the dielectric layer (102), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

摘要翻译： 本发明提供一种电容元件（100）的制造方法，设置有作为电容元件（100）的第一电极层的基板（101），将作为电极层设置的基板（101）进行调理， 层（102）沉积在经调理的基底（101）上，并且第二电极层（104）被施加在所产生的层叠层上，通过热处理改变层堆叠，使得介电层（102）沉积 在调理衬底（101）上形成电介质混合层（105），其上沉积有介电层（102）上的反应层（103），该电介质混合层具有增加的介电常数（k）或增加的热稳定性。

公开(公告)号：US20070052069A1

公开(公告)日：2007-03-08

申请号：US11362384

申请日：2006-02-24

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L29/40 ,  G08B13/14

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L23/5225 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated conductor arrangement comprises a substrate with a top side, at least one tubular conductor trench provided in the substrate below the top side of the substrate and a conductor. The conductor comprises at least one tubular conductor layer and is integrated in the conductor trench.

摘要翻译： 集成导体布置包括具有顶侧的基板，设置在基板的下侧的基板中的至少一个管状导体沟槽和导体。 导体包括至少一个管状导体层并且集成在导体沟槽中。

公开(公告)号：US20070037349A1

公开(公告)日：2007-02-15

申请号：US11526788

申请日：2006-09-25

申请人： Martin Gutsche ,  Harald Seidl ,  Peter Moll

发明人： Martin Gutsche ,  Harald Seidl ,  Peter Moll

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/1085

摘要： To form a semiconductor device, a plurality of upwardly extending conductors can be formed. The conductors extend outward from a surface of a semiconductor body, adjacent ones of the conductors being separated from each other by a separating material. At least one support structure is formed between adjacent ones of the upwardly extending conductors. The support structure is formed of a material different than the separating material. The separating material can be removed and further processing can be performed on the semiconductor device.

摘要翻译： 为了形成半导体器件，可以形成多个向上延伸的导体。 导体从半导体本体的表面向外延伸，相邻的导体通过分离材料相互分离。 在相邻的向上延伸的导体之间形成至少一个支撑结构。 支撑结构由与分离材料不同的材料形成。 可以去除分离材料并且可以在半导体器件上进行进一步的处理。

公开(公告)号：US20060172489A1

公开(公告)日：2006-08-03

申请号：US11044721

申请日：2005-01-28

申请人： Harald Seidl ,  Martin Gutsche ,  Shrinivas Govindarajan

发明人： Harald Seidl ,  Martin Gutsche ,  Shrinivas Govindarajan

IPC分类号： H01L21/8242 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0228 ,  C23C16/34 ,  C23C16/40 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/3141 ,  H01L21/3143 ,  H01L27/1087 ,  H01L28/91 ,  H01L29/66181

摘要： Method for producing a dielectric material on a semiconductor device with an atomic layer deposition procedure, whereby an aluminum oxide nitride or a silicon oxide nitride or an aluminum silicon oxide nitride layer is deposited comprising a rare earth metal-element. The invention describes a semiconductor device with a dielectric layer comprising aluminum oxide nitride or silicon oxide nitride or an aluminum silicon oxide nitride comprising a rare earth metal element.

摘要翻译： 在具有原子层沉积程序的半导体器件上制造电介质材料的方法，由此沉积包含稀土金属元素的氧化铝氮化物或氧化硅氮化物或氧化铝氮化硅层。 本发明描述了具有包括氧化铝氮化物或氧化硅氮化物的介电层的半导体器件或包含稀土金属元素的铝氧化硅氮化物。

公开(公告)号：US20060094233A1

公开(公告)日：2006-05-04

申请号：US11256300

申请日：2005-10-21

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for determining an edge coverage during coating processes a substrate is provided, a mask layer is deposited on the substrate, at least one through hole is formed in the mask layer and at least one first trench-type depression is formed in the substrate by patterning the substrate and the mask layer. An expanded second trench-type depression which extends in a direction parallel to the surface of the substrate is obtained by expanding isotropically the first trench-type depression. The second trench-type depression comprises a lateral trench opening at at least one lateral end region so that a coating material can penetrate laterally into the second trench-type depression through the trench opening.

摘要翻译： 在涂覆工艺中确定边缘覆盖度的方法中，提供了一种衬底，掩模层沉积在衬底上，在掩模层中形成至少一个通孔，并在衬底中形成至少一个第一沟槽型凹陷 通过图案化基板和掩模层。 通过各向同性地扩展第一沟槽型凹陷，获得沿与基板表面平行的方向延伸的扩展的第二沟槽型凹陷。 第二沟槽式凹陷包括在至少一个侧向端部区域处的横向沟槽开口，使得涂层材料可以通过沟槽开口横向穿过第二沟槽型凹陷。

公开(公告)号：US08420526B2

公开(公告)日：2013-04-16

申请号：US13167744

申请日：2011-06-24

申请人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

发明人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC分类号： H01L21/4763

CPC分类号： H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

公开(公告)号：US20120305873A1

公开(公告)日：2012-12-06

申请号：US13591247

申请日：2012-08-22

申请人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

发明人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC分类号： H01L45/00

CPC分类号： H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

摘要翻译： 本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂， 随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

公开(公告)号：US08084190B2

公开(公告)日：2011-12-27

申请号：US12548723

申请日：2009-08-27

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/027 ,  H01L21/033 ,  C23F1/02

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/30604

摘要： A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures.

摘要翻译： 提供了用于提供亚光刻结构的层结构和工艺。 在载体层的表面上形成第一辅助层。 在第一辅助层的表面上形成光刻图案化的第二辅助层结构。 使用图案化的第二辅助层结构作为掩模对第一辅助层进行各向异性蚀刻，以形成各向异性图案化的第一辅助层结构。 各向异性图案化的第一辅助层结构使用图案化的第二辅助层结构进行各向同性地回蚀，以除去第二辅助层结构之下的部分并形成各向同性图案化的第一辅助层结构。 掩模层形成在载体层上，包括第二辅助层结构下面的子部分，并且各向异性地向下蚀刻到载体层以形成亚光刻结构。 去除第一和第二辅助层结构以露出​​亚光刻结构。