公开(公告)号：US20070037349A1

公开(公告)日：2007-02-15

申请号：US11526788

申请日：2006-09-25

申请人： Martin Gutsche ,  Harald Seidl ,  Peter Moll

发明人： Martin Gutsche ,  Harald Seidl ,  Peter Moll

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/1085

摘要： To form a semiconductor device, a plurality of upwardly extending conductors can be formed. The conductors extend outward from a surface of a semiconductor body, adjacent ones of the conductors being separated from each other by a separating material. At least one support structure is formed between adjacent ones of the upwardly extending conductors. The support structure is formed of a material different than the separating material. The separating material can be removed and further processing can be performed on the semiconductor device.

摘要翻译： 为了形成半导体器件，可以形成多个向上延伸的导体。 导体从半导体本体的表面向外延伸，相邻的导体通过分离材料相互分离。 在相邻的向上延伸的导体之间形成至少一个支撑结构。 支撑结构由与分离材料不同的材料形成。 可以去除分离材料并且可以在半导体器件上进行进一步的处理。

公开(公告)号：US07456461B2

公开(公告)日：2008-11-25

申请号：US11112940

申请日：2005-04-22

申请人： Martin Gutsche ,  Harald Seidl ,  Peter Moll

发明人： Martin Gutsche ,  Harald Seidl ,  Peter Moll

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10817 ,  H01L27/10814 ,  H01L28/90

摘要： The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

摘要翻译： 本发明涉及叠层电容器阵列和叠层电容器阵列的制造方法，所述层叠电容器阵列具有多个层叠的电容器，绝缘体保持至少两个彼此间隔开的相邻叠层电容器，使得它们之间不会发生电接触， 电容器机械稳定。

公开(公告)号：US06774005B2

公开(公告)日：2004-08-10

申请号：US10206303

申请日：2002-07-26

申请人： Martin Gutsche ,  Peter Moll ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

发明人： Martin Gutsche ,  Peter Moll ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  C23C16/32 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28556

摘要： At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal carbide layer is formed by depositing an alternating sequence of metal-containing layers and carbon-containing layers on top of one another and then subjecting them to a heat treatment, in such a manner that they mix with one another. The patterning of the layer sequence can be carried out before the carbide formation step.

摘要翻译： 上部电容器电极的至少一部分层由金属碳化物形成，优选由过渡金属碳化物形成。 在一个实施方案中，金属碳化物层通过在彼此顶部沉积含金属层和含碳层的交替序列形成，然后使它们以彼此混合的方式进行热处理。 层序列的图案化可以在碳化物形成步骤之前进行。

公开(公告)号：US09177995B2

公开(公告)日：2015-11-03

申请号：US13591247

申请日：2012-08-22

申请人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

发明人： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC分类号： H01L27/10 ,  H01L27/24 ,  H01L21/285 ,  H01L27/108 ,  B82Y10/00 ,  H01L21/768 ,  H01L27/22

CPC分类号： H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

摘要： The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

摘要翻译： 本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂， 随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

公开(公告)号：US07317201B2

公开(公告)日：2008-01-08

申请号：US11296740

申请日：2005-12-07

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

摘要： In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.

摘要翻译： 在制造微电子电极结构体的方法中，制备第一布线面，设置第一布线面上的绝缘区域，形成绝缘区域的贯通孔，形成通孔内的环状电极， 在绝缘区域上形成第二布线平面。 环形电极包括第一侧和第二侧，环形电极在第一侧电连接到第一布线平面，并且第二布线平面电连接到环形电极的第二侧。

公开(公告)号：US20060204898A1

公开(公告)日：2006-09-14

申请号：US11361849

申请日：2006-02-23

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： G03F7/00

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/30604

摘要： A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures.

公开(公告)号：US20060186480A1

公开(公告)日：2006-08-24

申请号：US11061314

申请日：2005-02-18

申请人： Harald Seidl ,  Josef Willer ,  Martin Gutsche

发明人： Harald Seidl ,  Josef Willer ,  Martin Gutsche

IPC分类号： H01L31/072 ,  H01L21/8238

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/4234

摘要： A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.

摘要翻译： 提供薄SiGe层作为附加的下栅电极层，并且布置在薄栅极氧化物和栅电极层之间，优选多晶硅。 SiGe层可以选择性地蚀刻到栅电极和栅极氧化物，并且在源极/漏极区附近被横向去除以形成凹槽，随后填充适合于电荷捕获的材料。 器件结构和制造方法适用于包括存储器单元的本地互连，CMOS逻辑外围和补偿阵列和外围中的层级差异的装置的集成方案。

公开(公告)号：US20050245027A1

公开(公告)日：2005-11-03

申请号：US11079131

申请日：2005-03-14

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/82

摘要： The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain second directions (4), comprising the following method steps: provision of an auxiliary layer stack (5) having first auxiliary layers (6) with a predetermined etching rate and at least one second auxiliary layer (7) with a higher etching rate on a substrate (8); etching of in each case one hollow cylinder (9) for each stacked capacitor (2) through the auxiliary layer stack (5) in accordance with the regular arrangement, with the auxiliary layer stack (5) being left in place in intermediate regions (10) between the hollow cylinders (9); isotropic etching of the second auxiliary layers (7) to form widened portions (11) of the hollow cylinders (9), without any second auxiliary layer (7) being left in place between in each case two hollow cylinders (9) which adjoin one another in the first direction (3) and with a second residual auxiliary layer (7a) being left in place between in each case two hollow cylinders (9) which adjoin one another in the second direction (4); conformal deposition of an insulator layer (12) in order to completely fill the widened portions (11); deposition of a first electrode layer (13) in the hollow cylinders (9) in order to form the stacked capacitors (2); filling of the hollow cylinders (9) with a first filling (14); removal of the first auxiliary layers (6), the second residual auxiliary layers (7a) and the first filling (14) and completion of the stacked capacitor array (1).

公开(公告)号：US06949269B2

公开(公告)日：2005-09-27

申请号：US10690002

申请日：2003-10-21

申请人： Harald Seidl ,  Martin Gutsche

发明人： Harald Seidl ,  Martin Gutsche

IPC分类号： C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  B05D1/36

CPC分类号： C23C16/45523 ,  C23C16/0281 ,  C23C16/045 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/31612 ,  H01L27/1087 ,  H01L29/66181

摘要： A method is taught for fabricating patterned silicon dioxide layers on process areas disposed perpendicularly or at an inclination to a substrate surface. Firstly, a starter layer having leaving groups is produced by non-conformal deposition of a reactive component. Tris(tert-butoxy)silanol is subsequently added. The addition of the tris(tert-butoxy)silanol leads to the formation of a silicon dioxide layer selectively only on the starter layer.

摘要翻译： 教导了一种用于在垂直于或者倾斜于衬底表面设置的工艺区域上制造图案化二氧化硅层的方法。 首先，通过反应性组分的非共形沉积产生具有离去基团的起始层。 随后加入三（叔丁氧基）硅烷醇。 三（叔丁氧基）硅烷醇的加入导致仅在引发剂层上形成二氧化硅层。

公开(公告)号：US06916704B2

公开(公告)日：2005-07-12

申请号：US10167800

申请日：2002-06-12

申请人： Martin Gutsche ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

发明人： Martin Gutsche ,  Bernhard Sell ,  Annette Sänger ,  Harald Seidl

IPC分类号： C23C14/58 ,  C23C16/56 ,  H01L21/20 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/334 ,  H01L21/44 ,  H01L21/461 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L29/945

摘要： An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

摘要翻译： 作为DRAM存储单元的沟槽电容器的上电容器电极，至少部分地由多个含金属层沉积在另一层之上而形成，并且在每种情况下在被沉积之后被调节。 以这种方式，可以减小电极层的内应力，因此可以提高沟槽电容器的断裂强度和耐漏电流。