公开(公告)号：US5708801A

公开(公告)日：1998-01-13

申请号：US744387

申请日：1996-11-07

申请人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

发明人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

IPC分类号： G06F1/06 ,  G06F13/42 ,  G06F1/12

CPC分类号： G06F1/06 ,  G06F13/4217

摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N是 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

公开(公告)号：US5530933A

公开(公告)日：1996-06-25

申请号：US201463

申请日：1994-02-24

申请人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

发明人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0831

摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

摘要翻译： 与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。 每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。 每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。 每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。 当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

公开(公告)号：US4226641A

公开(公告)日：1980-10-07

申请号：US879042

申请日：1978-02-21

申请人： Howard E. Bode, Sr. ,  James B. Williams

发明人： Howard E. Bode, Sr. ,  James B. Williams

IPC分类号： D06G1/00 ,  B08B1/02 ,  B08B1/04

CPC分类号： D06G1/00

摘要： A rug or mat cleaning system is disclosed which is comprised of first a dry lint and dust removing section, then a water or like liquid containing vessel having an initial wash section and then a rinse section and then finally a wringer section. A mat to be cleaned is passed through a first conveying roller at a slower driving speed. Thereafter, the mat or rug enters an increased speed brush which both removes dirt and agitates the surface of the rug and beats it to knock loose undesireable dirt and like particles. In the wash section of the system, alternating feed rollers and brush rollers carry the mat or rug to be cleaned. Each feed roller clamps and holds the rug to prevent slipping while conveying it at a slower linear speed. Each brush roller provides a brushing surface having a substantially higher linear speed than the surface of the conveying rolls. Thus, a "tuck" or crease is created in the rug between each high speed roller brush and its adjacent and following slower conveying roll. A wringer is provided at the end of the system to remove extraneous water from the rug after its cleansing. Pressure belts are provided above the cleaning brushes for enhanced cleaning and operation. A special beater roller with projecting ridges is also included.

摘要翻译： 公开了一种地毯或垫子清洁系统，其首先包括干燥的棉绒和除尘部分，然后包括具有初始洗涤部分，然后是冲洗部分，然后最后是绞合器部分的含水容器的容器。 要清洁的垫子以较慢的驱动速度通过第一输送辊。 此后，垫子或地毯进入增加速度的刷子，它们都去除污垢并搅动地毯的表面，并打击它以敲入不想要的污垢和类似的颗粒。 在系统的洗涤部分，交替的进料辊和刷辊携带要清洁的垫子或毯子。 每个进给辊夹紧并保持地毯，以防止在以较慢的线速度输送时滑动。 每个刷辊提供具有比输送辊的表面大得多的线速度的刷洗表面。 因此，在每个高速辊刷及其相邻和随后较慢的输送辊之间的地毯中产生“褶皱”或褶皱。 系统末端设有螺旋桨，清洁后从地毯中除去多余的水分。 在清洁刷上方设有压力带，用于增强清洁和操作。 还包括一个特殊的带有凸脊的打浆辊。

公开(公告)号：US08862682B2

公开(公告)日：2014-10-14

申请号：US12707594

申请日：2010-02-17

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： G06F15/16 ,  H04L29/06

CPC分类号： H04L69/162 ,  H04L67/1097

摘要： An improved method of using sockets in connection with TCP over certain local networks, such as the enhanced Ethernet. In particular, an accelerated socket protocol is provided to enhance data communications between different host computer systems connected to an enhanced Ethernet network. Under the accelerated socket protocol, a host computer, while sending a number of data packets, is able to indicate a particular data packet is a last ready data packet out of all packets ready to be sent by setting a PUSH bit in that particular data packet, which triggers an automatic acknowledgement message that confirms receipt of data from the receiver. In addition, while receiving data packets, the host computer can advertise an effective window that corresponds to the actually available receiving space in the host computer.

摘要翻译： 在某些本地网络（如增强型以太网）上使用与TCP连接的套接字的改进方法。 特别地，提供加速套接字协议以增强连接到增强型以太网的不同主机计算机系统之间的数据通信。 在加速套接字协议下，主计算机在发送多个数据包的同时，能够通过在该特定数据包中设置一个PUSH位来指示特定数据包是准备发送的所有数据包中的最后一个准备好的数据包 ，其触发确认从接收器接收数据的自动确认消息。 此外，在接收数据分组的同时，主计算机可以发布对应于主计算机中实际可用的接收空间的有效窗口。

公开(公告)号：US08774215B2

公开(公告)日：2014-07-08

申请号：US11514665

申请日：2006-09-01

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： H04L12/50

CPC分类号： H04L29/06068 ,  H04L12/4633 ,  H04L29/12028 ,  H04L29/12886 ,  H04L61/103 ,  H04L61/6045 ,  H04L69/22

摘要： The use of Ethernet as an underlying transport for Fiber Channel (FC) frames is disclosed in the Fiber Channel Over Ethernet (FCOE) protocol. In FCOE, the FC physical layer and part of the FC-2 link layer are replaced with the Ethernet physical and link layers. Each FC frame is encapsulated within an Ethernet Frame. The payload of the FCOE frame contains type information from the FC Start Of Frame (SOF) indicator, the FC header, an optional FC payload, and type information from the FC End Of Frame (EOF) indicator. In one embodiment, an Ethernet network carrying FCOE replaces a standard FC network. In another embodiment, devices implementing FCOE may be implemented in a blade server. The entire backplane is Ethernet, over which both storage and networking traffic can be run. The Ethernet links are connected to an Ethernet switch, a FCOE/FC converter, and a FC switch.

摘要翻译： 在以太网光纤通道（FCOE）协议中公布了以太网作为光纤​​通道（FC）帧的底层传输的使用。 在FCOE中，FC物理层和FC-2链路层的一部分被以太网物理层和链路层替代。 每个FC帧封装在以太网帧中。 FCOE帧的有效载荷包含来自FC起始帧（SOF）指示符，FC头，可选FC有效载荷和FC帧结束（EOF）指示符的类型信息的类型信息。 在一个实施例中，携带FCOE的以太网网络替代标准FC网络。 在另一个实施例中，实现FCOE的设备可以在刀片服务器中实现。 整个背板是以太网，可以运行存储和网络流量。 以太网链路连接到以太网交换机，FCOE / FC转换器和FC交换机。

公开(公告)号：US07673074B1

公开(公告)日：2010-03-02

申请号：US10421495

申请日：2003-04-22

申请人： Bino J. Sebastian ,  James B. Williams ,  Harold E. Roman ,  Richard F. Prohaska

发明人： Bino J. Sebastian ,  James B. Williams ,  Harold E. Roman ,  Richard F. Prohaska

IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/177

CPC分类号： H04L69/16 ,  H04L69/12 ,  H04L69/161

摘要： The avoidance of port collisions in a hardware-accelerated network protocol, such as Transmission Control Protocol (TCP)/Internet Protocol (IP), is disclosed. In one example, a hardware-accelerated host bus adaptor (HBA) offloads protocol processing from a host computer's operating system. However, a port collision occurs if a non-accelerated host TCP/IP stack and a hardware accelerated host bus adapter TCP/IP stack choose the same port for establishing a network connection. In a double-ended TCP/IP acceleration connection, a unique TCP port is bound to the accelerated TCP/IP stack. In a single-ended TCP/IP acceleration connection, either the host TCP/IP stack is prevented from using that port or a non-accelerated connection is associated with an accelerated connection without binding a port.

摘要翻译： 披露了在硬件加速网络协议（如传输控制协议（TCP）/网际协议（IP））中避免端口冲突。 在一个示例中，硬件加速主机总线适配器（HBA）从主机的操作系统卸载协议处理。 但是，如果非加速主机TCP / IP堆栈和硬件加速主机总线适配器TCP / IP堆栈选择相同的端口建立网络连接，则会发生端口冲突。 在双端TCP / IP加速连接中，唯一的TCP端口绑定到加速TCP / IP堆栈。 在单端TCP / IP加速连接中，禁止主机TCP / IP堆栈使用该端口，或者非加速连接与加速连接相关联，而不绑定端口。

公开(公告)号：US20080056300A1

公开(公告)日：2008-03-06

申请号：US11514665

申请日：2006-09-01

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： H04J3/16

CPC分类号： H04L29/06068 ,  H04L12/4633 ,  H04L29/12028 ,  H04L29/12886 ,  H04L61/103 ,  H04L61/6045 ,  H04L69/22

摘要： The use of Ethernet as an underlying transport for Fibre Channel (FC) frames is disclosed in the Fibre Channel Over Ethernet (FCOE) protocol. In FCOE, the FC physical layer and part of the FC-2 link layer are replaced with the Ethernet physical and link layers. Each FC frame is encapsulated within an Ethernet Frame. The payload of the FCOE frame contains type information from the FC Start Of Frame (SOF) indicator, the FC header, an optional FC payload, and type information from the FC End Of Frame (EOF) indicator. In one embodiment, an Ethernet network carrying FCOE replaces a standard FC network. In another embodiment, devices implementing FCOE may be implemented in a blade server. The entire backplane is Ethernet, over which both storage and networking traffic can be run. The Ethernet links are connected to an Ethernet switch, a FCOE/FC converter, and a FC switch.

摘要翻译： 在以太网光纤通道（FCOE）协议中公布了以太网作为光纤​​通道（FC）帧的底层传输的使用。 在FCOE中，FC物理层和FC-2链路层的一部分被以太网物理层和链路层替代。 每个FC帧封装在以太网帧中。 FCOE帧的有效载荷包含来自FC起始帧（SOF）指示符，FC头，可选FC有效载荷和FC帧结束（EOF）指示符的类型信息的类型信息。 在一个实施例中，携带FCOE的以太网网络替代标准FC网络。 在另一个实施例中，实现FCOE的设备可以在刀片服务器中实现。 整个背板是以太网，可以运行存储和网络流量。 以太网链路连接到以太网交换机，FCOE / FC转换器和FC交换机。

公开(公告)号：US07283471B2

公开(公告)日：2007-10-16

申请号：US10386642

申请日：2003-03-11

申请人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

发明人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

IPC分类号： H04L1/00

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US06570850B1

公开(公告)日：2003-05-27

申请号：US09065118

申请日：1998-04-23

申请人： Maria C. Gutierrez ,  Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  Harold E. Roman ,  James B. Williams

发明人： Maria C. Gutierrez ,  Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  Harold E. Roman ,  James B. Williams

IPC分类号： H04Q1104

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US06182176B2

公开(公告)日：2001-01-30

申请号：US08201185

申请日：1994-02-24

申请人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Craig R. Frink ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  John L. Wood

发明人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Craig R. Frink ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  John L. Wood

IPC分类号： G06F1314

CPC分类号： G06F13/36

摘要： A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

摘要翻译： 共享总线系统，其具有总线和耦合到总线的一组客户端模块。 每个客户端模块都能够将总线上的事务发送到其他客户端模块，并从其他客户端模块接收总线上的事务处理。 每个模块都有一个队列，用于存储由模块接收的事务处理。 总线控制器限制可以在总线上发送的事务的类型，以防止任何模块的队列溢出。