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    Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers
    35.
    发明授权
    Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers 有权
    使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低

    公开(公告)号：US07521776B2

    公开(公告)日：2009-04-21

    申请号：US11618346

    申请日：2006-12-29

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L29/04

    CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

    摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

    摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

    SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE
    36.
    发明申请
    SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 失效
    用于半导体器件中的屏蔽带电充电的低温隔离结构

    公开(公告)号：US20070187778A1

    公开(公告)日：2007-08-16

    申请号：US11276132

    申请日：2006-02-15

    申请人： Ethan Cannon ,  Shunhua Chang ,  Toshiharu Furukawa ,  David Horak ,  Charles Koburger

    发明人： Ethan Cannon ,  Shunhua Chang ,  Toshiharu Furukawa ,  David Horak ,  Charles Koburger

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76224 ,  H01L29/7833

    摘要： A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

    摘要翻译： 一种用于形成半导体结构的半导体结构和相关方法。 半导体结构包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构。 第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。 沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。 导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

    Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes
    37.
    发明申请
    Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes 审中-公开
    集成电路芯片利用由碳纳米管形成的定向圆柱形空隙的介电层

    公开(公告)号：US20070184647A1

    公开(公告)日：2007-08-09

    申请号：US11735988

    申请日：2007-04-16

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L21/4763

    CPC分类号： B82Y10/00 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

    摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

    摘要翻译： 集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。 优选地，通过首先形成垂直于集成电路晶片的表面的多个相对长的薄碳纳米管，在围绕碳纳米管的表面上沉积常规电介质，然后除去碳纳米管以产生空隙来形成空隙。 由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。 用于导体的电介质中形成的凹陷衬有非共形绝缘膜以密封空隙。 使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

    Methods and semiconductor structures for latch-up suppression using a conductive region
    38.
    发明申请
    Methods and semiconductor structures for latch-up suppression using a conductive region 失效
    使用导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US20070170543A1

    公开(公告)日：2007-07-26

    申请号：US11340752

    申请日：2006-01-26

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0921 ,  H01L21/823878 ,  H01L29/78

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。 在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。 沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。 可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

    Methods and semiconductor structures for latch-up suppression using a buried conductive region
    40.
    发明申请
    Methods and semiconductor structures for latch-up suppression using a buried conductive region 失效
    使用掩埋导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US20070158755A1

    公开(公告)日：2007-07-12

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    发明人： Shunhua Chang ,  Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁接壤的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。