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    Methods of forming alternating phase shift masks having improved phase-shift tolerance
    3.
    发明申请
    Methods of forming alternating phase shift masks having improved phase-shift tolerance 失效
    形成具有改进的相移公差的交替相移掩模的方法

    公开(公告)号：US20050202322A1

    公开(公告)日：2005-09-15

    申请号：US10798908

    申请日：2004-03-11

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00

    CPC分类号： G03F1/30

    摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

    摘要翻译： 用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。 所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。 图案层从手柄晶片转移到掩模板。 相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。 特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

    Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes
    4.
    发明申请
    Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes 审中-公开
    集成电路芯片利用由碳纳米管形成的定向圆柱形空隙的介电层

    公开(公告)号：US20070184647A1

    公开(公告)日：2007-08-09

    申请号：US11735988

    申请日：2007-04-16

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L21/4763

    CPC分类号： B82Y10/00 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

    摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

    摘要翻译： 集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。 优选地，通过首先形成垂直于集成电路晶片的表面的多个相对长的薄碳纳米管，在围绕碳纳米管的表面上沉积常规电介质，然后除去碳纳米管以产生空隙来形成空隙。 由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。 用于导体的电介质中形成的凹陷衬有非共形绝缘膜以密封空隙。 使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

    Integrated circuit chip utilizing oriented carbon nanotube conductive layers
    5.
    发明申请
    Integrated circuit chip utilizing oriented carbon nanotube conductive layers 失效
    集成电路芯片利用定向碳纳米管导电层

    公开(公告)号：US20060022221A1

    公开(公告)日：2006-02-02

    申请号：US10901858

    申请日：2004-07-29

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L29/768

    CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

    摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

    摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

    Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers
    6.
    发明申请
    Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 失效
    集成电路芯片利用定向碳纳米管导电层

    公开(公告)号：US20080042287A1

    公开(公告)日：2008-02-21

    申请号：US11924894

    申请日：2007-10-26

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L23/52

    CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

    摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

    摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

    Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers
    7.
    发明申请
    Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 有权
    集成电路芯片利用定向碳纳米管导电层

    公开(公告)号：US20070048879A1

    公开(公告)日：2007-03-01

    申请号：US11552771

    申请日：2006-10-25

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L21/00

    CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

    摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

    摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

    DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS)
    8.
    发明申请
    DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS) 失效
    双栅FET（场效应晶体管）

    公开(公告)号：US20060172496A1

    公开(公告)日：2006-08-03

    申请号：US10905979

    申请日：2005-01-28

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

    摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

    摘要翻译： 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

    METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY
    10.
    发明申请
    METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY 有权
    制备垂直碳纳米管场效应晶体管的方法在阵列和场效应晶体管中的布置及其形成的阵列

    公开(公告)号：US20080044954A1

    公开(公告)日：2008-02-21

    申请号：US11926627

    申请日：2007-10-29

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： H01L21/8234

    CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

    摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

    摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。