公开(公告)号：US20080194220A1

公开(公告)日：2008-08-14

申请号：US12068525

申请日：2008-02-07

申请人： Jun Suzuki

发明人： Jun Suzuki

IPC分类号： H04B1/16 ,  H04B1/10

CPC分类号： H04B1/10

摘要： An FM receiver that is suitable for reducing a transmission bandwidth WF of a bandpass filter to remove adjacent-channel interference, and increasing WF to prevent audio distortion. A detection output signal SOUT is inputted to an HPF 122 when a reception electric field strength signal SM-DC indicates an intermediate or stronger electric field. In a weak electric field, an AC component signal SM-AC, which is extracted from an intermediate signal SIF1 prior to detection and which has fewer high-pass noise components than SOUT, is inputted to the HPF 122. A control circuit 120 detects a case as an adjacent-channel interference state when a large amount of high-pass components passes through the HPF 122, and reduces WF of an IFBPF 70 in order to remove adjacent-channel interference. When a small amount of high-pass components is transmitted, WF is increased in order to minimize audio distortion.

摘要翻译： 一种FM接收机，适于减少带通滤波器的传输带宽W SUB以消除相邻信道干扰，并增加W SUB以防止音频失真。 当接收电场强度信号S M-DC <>表示中间或更强的电场时，检测输出信号S OUT OUT被输入到HPF 122。 在弱电场中，在检测之前从中间信号S IF1＆lt; 1＆gt;提取并且具有较少的高通噪声分量的AC分量信号S M-AC＆lt; 输入到HPF 122.当大量的高通分量通过HPF 122时，控制电路120将情况检测为相邻信道干扰状态，并且减少W 为了去除相邻信道干扰，IFBPF70的 。 当发送少量的高通分量时，为了最小化音频失真，增加了W >F 。

公开(公告)号：USD569342S1

公开(公告)日：2008-05-20

申请号：US29269539

申请日：2006-12-01

申请人： Jun Suzuki

设计人： Jun Suzuki

公开(公告)号：US20080040526A1

公开(公告)日：2008-02-14

申请号：US11836357

申请日：2007-08-09

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Atsushi Iwata

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Atsushi Iwata

IPC分类号： G06F13/00

CPC分类号： G06F13/4081 ,  G06F2213/0026

摘要： A virtual PCI Express device 1600 indicates the presence of a pseudo I/O device in a PCI Express initial configuration cycle to reserve a resource space for a device anticipated to be installed in the future, and when an I/O device 1400 is inserted into an unoccupied slot 1605, a virtual PCI Express device control logic 1602 notifies a downstream PCI-PCI bridge 1504 via a hot-plugging control line 1601, and the downstream PCI-PCI bridge 1504 generates an interrupt to a CPU 1100 to notify it of insertion of the I/O device 1400 in conformance with the procedure for hot plugging defined by the PCI-SIG Standards, and configuration software 1000 invoked configures the inserted I/O device 1400.

摘要翻译： 虚拟PCI Express设备1600指示在PCI Express初始配置周期中存在伪I / O设备以为将来预期安装的设备预留资源空间，并且当将I / O设备1400插入时 未占用的时隙1605，虚拟PCI Express设备控制逻辑1602经由热插拔控制线1601通知下游PCI-PCI桥1504，并且下游PCI-PCI桥1504向CPU 1100产生中断以通知其插入 的I / O设备1400符合由PCI-SIG标准定义的热插拔程序，并且配置软件1000被调用配置所插入的I / O设备1400。

公开(公告)号：US20080026251A1

公开(公告)日：2008-01-31

申请号：US11826495

申请日：2007-07-16

申请人： Jun Suzuki ,  Kenji Yoneda ,  Seiji Matsuyama

发明人： Jun Suzuki ,  Kenji Yoneda ,  Seiji Matsuyama

IPC分类号： H01L21/31 ,  B32B9/00 ,  C23C16/00

CPC分类号： H01L21/3141 ,  C23C16/405 ,  C23C16/45504 ,  C23C16/45546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/31608 ,  H01L21/31645 ,  H01L21/3185

摘要： In an insulating film formation method, a cycle A in which O3 at a low flow rate is supplied onto a substrate and then O3 supplied is allowed to react with Hf on the substrate in a non-equilibrium state to form a hafnium oxide film is carried out M times (M≧1), and a cycle B in which O3 at a high flow rate is supplied onto the substrate and then O3 supplied is allowed to react with Hf on the substrate in an equilibrium state to form a hafnium oxide film is carried out N times (N≧1). These insulating film formation cycles are defined as one sequence. This sequence is repeated until a desired thickness is obtained, thereby forming a target insulating film.

摘要翻译： 在绝缘膜形成方法中，将其中以低流量供给O 3 N的循环A供应到基板上，然后将所提供的O 3与Hf反应， 在非平衡状态下形成氧化铪膜的衬底进行M次（M> = 1），并且以高流速将O 3 3的循环B供给到 将底物和然后使O 3在平衡状态下与Hf在基板上反应以形成氧化铪膜N次（N> = 1）。 这些绝缘膜形成循环被定义为一个顺序。 重复该顺序，直到获得所需的厚度，从而形成目标绝缘膜。

公开(公告)号：US20080023669A1

公开(公告)日：2008-01-31

申请号：US11629948

申请日：2005-06-15

申请人： Toru Imori ,  Jun Suzuki ,  Kazunori Iida

发明人： Toru Imori ,  Jun Suzuki ,  Kazunori Iida

IPC分类号： C09K3/00 ,  C08K3/08

CPC分类号： D07B1/0666 ,  C08K5/16 ,  C09D4/00 ,  C09D7/63 ,  C09D183/08 ,  C23C2222/20 ,  C08G77/26

摘要： A surface treatment agent for metal is provided which is capable of improving the strength of adhesion between metal and rubber. A metal surface treatment agent for promoting adhesion between the metal and rubber comprising a cobalt or other metal compound and a silane coupling agent having a metal-capturing functional group in the molecule, and a metal surface treatment agent for promoting adhesion between the metal and rubber comprising a silane coupling agent having in the molecule a metal-capturing functional group with a captured metal such as a cobalt. The metal-capturing functional group is preferably an amino, amide or azole group.

摘要翻译： 提供了一种能够提高金属与橡胶之间的粘合强度的金属表面处理剂。 一种金属表面处理剂，用于促进包含钴或其它金属化合物的金属和橡胶之间的粘合性和在分子中具有金属捕获官能团的硅烷偶联剂，以及金属表面处理剂，用于促进金属和橡胶之间的粘合 包括在分子中具有捕获金属如钴的金属捕获官能团的硅烷偶联剂。 金属捕获官能团优选为氨基，酰胺或唑基。

公开(公告)号：US20070278589A1

公开(公告)日：2007-12-06

申请号：US11654672

申请日：2007-01-18

申请人： Nobuyuki Tamura ,  Jun Suzuki

发明人： Nobuyuki Tamura ,  Jun Suzuki

IPC分类号： H01L31/00

CPC分类号： H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： A semiconductor device includes: an NMIS transistor on an NMIS region of a semiconductor substrate; a PMIS transistor on a PMIS region of the semiconductor substrate; and a stress dielectric film continuously provided on the semiconductor substrate to cover the NMIS transistor and PMIS transistor, the stress dielectric film having internal stress, wherein part of the stress dielectric film extending over the NMIS region has tensile internal stress compared to part of the stress dielectric film extending over the PMIS region.

摘要翻译： 半导体器件包括：在半导体衬底的NMIS区域上的NMIS晶体管; 在半导体衬底的PMIS区域上的PMIS晶体管; 以及在半导体衬底上连续地设置以覆盖NMIS晶体管和PMIS晶体管的应力介电膜，该应力介电膜具有内部应力，其中在NMIS区域上延伸的应力介电膜的部分具有与部分应力相比的拉伸内应力 电介质膜延伸在PMIS区域上。

公开(公告)号：US20070198763A1

公开(公告)日：2007-08-23

申请号：US11707084

申请日：2007-02-16

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： A PCI Express switch which connects a plurality of peripheral devices to an arbitrary one of a plurality of CPUs through an Ethernet is constituted by a plurality of upstream and downstream PCI Express-network bridges, an Ethernet switch, and a system manager. Each of the upstream and downstream PCI Express-network bridges includes a PCI Express adapter which terminates a link of a PCI Express bus, a network adapter which terminates a link to the Ethernet switch, and a control unit which encapsulates a TLP in a frame, the destination of which is a MAC address of a bridge to which the destination is connected to transmit and receive the frame. Because the switch according to the present invention comprising a plurality of upstream PCI Express-network bridges and a plurality of downstream PCI Express-network bridges connected to the plurality of upstream PCI Express network bridges through a network is equivalent to a conventional PCI Express switch, it is needless to change a conventional PCI software.

摘要翻译： 通过以太网将多个外围设备连接到多个CPU中的任意一个的PCI Express交换机由多个上游和下游PCI Express网络桥，以太网交换机和系统管理器构成。 上游和下游PCI Express网络桥接器中的每一个包括PCI Express适配器，其终止PCI Express总线的链路，终止到以太网交换机的链路的网络适配器以及将TLP封装在帧中的控制单元， 其目的地是目的地与之连接以发送和接收帧的网桥的MAC地址。 因为包括通过网络连接到多个上游PCI Express网桥的多个上游PCI Express网络桥和多个下游PCI Express网桥的根据本发明的交换机等同于传统的PCI Express交换机， 不用改变传统的PCI软件。

公开(公告)号：USD543503S1

公开(公告)日：2007-05-29

申请号：US29223554

申请日：2005-02-15

申请人： Jun Suzuki

设计人： Jun Suzuki

公开(公告)号：US20070097226A1

公开(公告)日：2007-05-03

申请号：US11582994

申请日：2006-10-19

申请人： Koji Shida ,  Jun Suzuki ,  Yoichi Kato ,  Hidehito Yamada ,  Akihito Nishizawa

发明人： Koji Shida ,  Jun Suzuki ,  Yoichi Kato ,  Hidehito Yamada ,  Akihito Nishizawa

IPC分类号： H04N5/228

CPC分类号： H04N5/335 ,  H04N5/2258

摘要： The invention is intended to reduce the number of parts constituting an image capturing system using a solid-state image sensor and reduce the size and cost of a mobile electronic appliance having camera functionality. An analog front end circuit for an image capturing system, which samples pixel readout signals input from a solid-state image sensor, amplifies the sampled signals up to a predetermined level, and converts the amplified signals into digital signals, is formed, together with a DSP for digital image processing and a CPU responsible for arithmetic processing and control for camera functionality such as auto focusing and register setting, in a semiconductor integrated circuit on a single semiconductor chip.

摘要翻译： 本发明旨在减少使用固态图像传感器构成图像捕获系统的部件的数量，并且减少具有相机功能的移动电子设备的尺寸和成本。 用于对从固态图像传感器输入的像素读出信号进行采样的图像捕获系统的模拟前端电路将采样信号放大到预定电平，并将放大的信号转换为数字信号，形成为 用于数字图像处理的DSP和负责在单个半导体芯片上的半导体集成电路中的用于诸如自动聚焦和寄存器设置的相机功能的算术处理和控制的CPU。

公开(公告)号：US20060006919A1

公开(公告)日：2006-01-12

申请号：US10995554

申请日：2004-11-24

申请人： Keiji Tanaka ,  Osamu Sarai ,  Fuminori Tanemura ,  Yoshito Date ,  Jun Suzuki

发明人： Keiji Tanaka ,  Osamu Sarai ,  Fuminori Tanemura ,  Yoshito Date ,  Jun Suzuki

IPC分类号： H03L5/00

CPC分类号： H03K17/223 ,  H03K3/356121 ,  H03K5/1506

摘要： A level shift circuit having a latch function includes a precharging PMOS transistor MP1 which is turned on in a precharge period to interrupt a through current of an input stage, an NMOS transistor MN1 which inputs data and performs discharging in a data input period, and a transistor MP2 for holding data after level shifting. Thus, each of the transistors can have a minimum configuration. Since the level shift circuit has a latch function, it is possible to omit a circuit for latching input data, thereby reducing a circuit area.

摘要翻译： 具有锁存功能的电平移位电路包括在预充电期间导通的中断输入级的通电的预充电PMOS晶体管MP1，在数据输入期间输入数据并进行放电的NMOS晶体管MN1， 以及用于在电平转换之后保持数据的晶体管MP2。 因此，每个晶体管可以具有最小的配置。 由于电平移位电路具有锁存功能，因此可以省略用于锁存输入数据的电路，从而减少电路面积。