公开(公告)号：US09359645B2

公开(公告)日：2016-06-07

申请号：US12585882

申请日：2009-09-28

申请人： Toshio Doi ,  Hideharu Abe

发明人： Toshio Doi ,  Hideharu Abe

IPC分类号： A61K31/00 ,  A61K38/00 ,  A61K39/395 ,  G01N33/53 ,  C12Q1/68 ,  A61K45/06

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。

公开(公告)号：US07901874B2

公开(公告)日：2011-03-08

申请号：US10571511

申请日：2004-09-09

申请人： Toshio Doi ,  Hideharu Abe

发明人： Toshio Doi ,  Hideharu Abe

IPC分类号： G01N33/48 ,  G01N33/50 ,  G01N33/53 ,  G01N33/68

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。

公开(公告)号：US07571639B2

公开(公告)日：2009-08-11

申请号：US11796996

申请日：2007-04-27

申请人： Toshio Doi ,  Kazutoshi Watanabe ,  Osamu Takaoka ,  Atsushi Uemoto

发明人： Toshio Doi ,  Kazutoshi Watanabe ,  Osamu Takaoka ,  Atsushi Uemoto

IPC分类号： H01J37/352

CPC分类号： G03F1/72 ,  G01Q10/06 ,  G01Q30/06 ,  G01Q80/00

摘要： An opaque defect is processed by scanning with a high load or height fixed mode using a probe harder than a pattern material of a photomask at the time of going scanning, and is observed by scanning with a low load or intermittent contact mode at the time of returning scanning so as to detect an ending point of the opaque defect by the height information. When there is a portion reaching to a glass substrate as an ending point, this portion is not scanned by the high load or height fixed mode in the next processing, and only a portion not reaching to the ending point is scanned by the high load or height fixed mode.

摘要翻译： 通过使用在扫描时比光掩模的图案材料更硬的探针，以高负载或高度固定模式进行扫描来处理不透明缺陷，并且通过在低负载或间歇接触模式下扫描来观察不透明缺陷 返回扫描，以便通过高度信息检测不透明缺陷的终点。 当到达玻璃基板的部分为终点时，在下一个处理中该部分不被高负载或高度固定模式扫描，并且只有未到达终点的部分被高负载扫描 高度固定模式。

公开(公告)号：US20080025967A1

公开(公告)日：2008-01-31

申请号：US10571511

申请日：2004-09-09

申请人： Toshio Doi ,  Hideharu Abe

发明人： Toshio Doi ,  Hideharu Abe

IPC分类号： A61K39/395 ,  A61K48/00 ,  A61P43/00 ,  C12Q1/48 ,  G01N33/53

CPC分类号： C12Q1/6883 ,  A61K45/06 ,  C07K16/2863 ,  C07K2317/76 ,  C12Q2600/106 ,  C12Q2600/158 ,  G01N33/6893 ,  G01N2333/4703 ,  G01N2333/4706 ,  G01N2333/51 ,  G01N2333/71

摘要： A method of detecting proliferative diseases causing sclerosis, comprising measuring the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1, phosphorylated Smad1, activin receptor-like kinase 1, activin receptor-like kinase 3 and bone morphogenetic proteins in a biological sample. A kit therefor. A prophylactic and/or therapeutic agent for proliferative diseases causing sclerosis, comprising as an active ingredient a substance having an inhibitory effect on the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A method of identifying substances effective in preventing and/or treating proliferative diseases causing sclerosis, comprising judging whether or not a test substance inhibits the expression of at least one substance selected from the group consisting of STAT3, phosphorylated STAT3, Smad1 and phosphorylated Smad1. A kit therefor.

摘要翻译： 一种检测引起硬化的增殖性疾病的方法，包括测量选自STAT3，磷酸化STAT3，Smad1，磷酸化Smad1，激活素受体样激酶1，激活素受体样激酶3和骨形态发生的至少一种物质的表达 生物样品中的蛋白质。 一个套件。 一种引起硬化的增殖性疾病的预防和/或治疗剂，其包含作为活性成分的对STAT3，磷酸化STAT3，Smad1和磷酸化Smad1中选择的至少一种物质的表达具有抑制作用的物质。 鉴定有效预防和/或治疗引起硬化的增殖性疾病的物质的方法，包括判断测试物质是否抑制至少一种选自STAT3，磷酸化STAT3，Smad1和磷酸化Smad1的物质的表达。 一个套件。

公开(公告)号：US5794020A

公开(公告)日：1998-08-11

申请号：US663982

申请日：1996-06-14

申请人： Akira Tanaka ,  Toshio Doi ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

发明人： Akira Tanaka ,  Toshio Doi ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

IPC分类号： H04L7/00 ,  G06F1/12 ,  H04L7/02 ,  H04L7/033 ,  H04L7/08

CPC分类号： H04L7/0337 ,  H04L7/0008 ,  H04L7/0041

摘要： A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.

摘要翻译： 第一可变延迟电路延迟从输入缓冲器输出的发送单元的接收数据，并将延迟的数据生成到数据未识别时间检测部分。 第一和第二锁存器分别在第三锁存器的锁存定时之前和之后以规则的间隔分别具有第二和第三可变延迟电路接收和输出的锁存定时。 在调整操作中，第二和第三可变延迟电路的延迟量被固定为足够小于传送周期的值，可变延迟电路的延迟量增加，判断电路检测到接收的前一边缘 数据，随后，第二和第三可变延迟电路的延迟量依次增加同时保持相同的值，并且检测接收数据的后沿。 在这种情况下，第三锁存器的定时被设置为最大裕量的最佳点。 在正常操作中，判断电路检测到与最佳点的偏差，并且根据检测精细地调整第一可变延迟电路的延迟量，从而将接收数据的锁存定时保持在最佳点。

公开(公告)号：US5715035A

公开(公告)日：1998-02-03

申请号：US667027

申请日：1996-06-20

申请人： Toshio Doi ,  Hiroshi Miyawaki

发明人： Toshio Doi ,  Hiroshi Miyawaki

IPC分类号： G03B27/32 ,  G03D15/00 ,  G03B27/52

CPC分类号： G03D15/005

摘要： A photographic printing apparatus includes a sorting apparatus comprising a plurality of receptacles for receiving negative films and prints which circulate in a closed loop path between a film loading station in close proximity to an exposure apparatus and a print loading station where prints, cut from a continuous web of photographic paper, are delivered. The receptacles are driven such that each receptacle related to a receptacle loaded with a specific negative film at the film loading station is positioned in the print loading station in time before a cluster of prints made from the specific negative film is delivered from the photographic printing apparatus.

摘要翻译： 一种照相打印装置，包括一个分拣装置，它包括多个接收器，用于接收负片和打印件，其在闭合环路中循环，所述封闭环路靠近曝光装置的胶片装载站和打印装置之间， 相纸纸，交付。 驱动容器使得与在装载位置处装载有特定负片的插座相关的每个插座在从特定负片制成的一组照片从照相打印设备传送之前的时间被定位在打印装载站中 。

公开(公告)号：US5394533A

公开(公告)日：1995-02-28

申请号：US869699

申请日：1992-04-16

申请人： Toshio Doi ,  Shigeo Mizugaki

发明人： Toshio Doi ,  Shigeo Mizugaki

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/14

CPC分类号： G06F12/0888 ,  G06F12/0864

摘要： A data cache, for use in a memory having an address space including tag addresses for identifying blocks of storage locations and a set of select addresses for identifying storage locations in a block, includes a set select decoder that decodes only a subset of said set of select addresses that identify sub-blocks of storage locations located at the upper and lower boundaries of a block. Thus, data in storage locations accessed by addresses near block boundaries which have a high number of bit transitions is registered to the cache so that the high number of bit transitions does not have to be driven on an external bus so that noise is reduced.

摘要翻译： 一种数据高速缓存，用于具有地址空间的存储器，该存储器包括用于标识存储位置的块的标签地址和用于识别块中的存储位置的一组选择地址，所述集合选择解码器仅对所述一组 选择标识位于块的上边界和下边界的存储位置的子块的地址。 因此，通过具有高数量位转换的块边界附近的地址访问的存储位置中的数据被登记到高速缓存，使得不必在外部总线上驱动高数量的位转换，从而降低噪声。

公开(公告)号：US5392416A

公开(公告)日：1995-02-21

申请号：US103791

申请日：1993-08-10

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

摘要翻译： 用于多处理器系统的集成电路结构的处理装置包括基于虚拟存储方案操作的执行单元和具有来自执行单元的逻辑地址指定的条目的高速缓冲存储器。 为了控制高速缓冲存储器，提供包含与高速缓冲存储器相同的逻辑地址指定的条目并存储用于高速缓存存储器的对应条目的控制信息的第一地址阵列与具有由物理地址指定的条目的第二地址阵列相关联， 将用于翻译物理地址的翻译信息存储到条目的逻辑地址。 当响应于外部提供的高速缓冲存储器无效请求输入要执行无效的物理地址时，通过使用物理地址对第二地址阵列进行访问，以从第二地址阵列获得翻译信息，从而生成 一个无效的逻辑地址。 通过使用所生成的逻辑地址对控制信息进行无效处理来访问第一地址阵列。

公开(公告)号：US5257361A

公开(公告)日：1993-10-26

申请号：US603620

申请日：1990-10-26

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

摘要翻译： 用于多处理器系统的集成电路结构的处理装置包括基于虚拟存储方案操作的执行单元和具有来自执行单元的逻辑地址指定的条目的高速缓冲存储器。 为了控制高速缓冲存储器，提供包含与高速缓冲存储器相同的逻辑地址指定的条目并存储用于高速缓存存储器的对应条目的控制信息的第一地址阵列与具有由物理地址指定的条目的第二地址阵列相关联， 将用于翻译物理地址的翻译信息存储到条目的逻辑地址。 当响应于外部提供的高速缓冲存储器无效请求输入要执行无效的物理地址时，通过使用物理地址对第二地址阵列进行访问，以从第二地址阵列获得翻译信息，从而生成 一个无效的逻辑地址。 通过使用所生成的逻辑地址对控制信息进行无效处理来访问第一地址阵列。

公开(公告)号：US5165010A

公开(公告)日：1992-11-17

申请号：US461080

申请日：1990-01-04

申请人： Noboru Masuda ,  Moritoshi Yasunaga ,  Minoru Yamada ,  Akira Masaki ,  Mitsuo Asai ,  Yuzo Hirai ,  Masayoshi Yagyu ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

发明人： Noboru Masuda ,  Moritoshi Yasunaga ,  Minoru Yamada ,  Akira Masaki ,  Mitsuo Asai ,  Yuzo Hirai ,  Masayoshi Yagyu ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).