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31.发明授权Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device 有权存储单元结构，采用这种存储单元结构的存储器件，以及具有这种存储器件的集成电路公开(公告)号：US08107290B2
公开(公告)日：2012-01-31
申请号：US12078547
申请日：2008-04-01
申请人： Yoonmyung Lee , Michael John Wieckowski , David Theodore Blaauw , Dennis Michael Chen Sylvester
发明人： Yoonmyung Lee , Michael John Wieckowski , David Theodore Blaauw , Dennis Michael Chen Sylvester
CPC分类号： G11C16/0416 , G11C16/0441 , G11C2216/10 , H01L27/0629 , H01L27/0805 , H01L27/11521 , H01L27/11526 , H01L27/11558 , H01L28/40
摘要： A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.
摘要翻译： 用于存储器件的存储单元结构包括具有浮置栅极节点的读取晶体管，隧穿电容器和耦合电容器堆叠。 隧道电容器连接到浮动栅极节点并具有第一编程端子，耦合电容器堆叠连接到浮动栅极节点并具有第二编程端子。 耦合电容器堆叠包括串联布置在浮动栅极节点和第二编程端子之间的至少两个耦合电容器，耦合电容器堆叠具有比隧道电容器更大的电容。 这样的存储单元结构在面积上是有效的，并且可以使用标准CMOS逻辑制造工艺来制造，从而避免了常规EEPROM和闪存器件的生产中涉及的一些复杂性。
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公开(公告)号：US07864562B2
公开(公告)日：2011-01-04
申请号：US12379820
申请日：2009-03-02
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.
摘要翻译： 集成电路存储器内的存储单元36具有耦合到第一传输门38和第二传输门40的访问控制器32.在对存储单元38的写访问期间，第一传输门38和第二传输门 40打开。 在读取访问期间，打开第一传递门38并关闭第二传递门40。 读写操作中的这种不对称允许形成存储单元36的门的不对称性，从而允许改变增加读稳健性和写鲁棒性。 不同栅极的设计参数中的不对称可以采取改变栅极长度，栅极宽度和阈值电压的形式，以便改变不同栅极的电导以适应其在存储单元36内的各自的作用 由分离的字线提供的非对称方式驱动读操作和写操作。
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公开(公告)号：US5790416A
公开(公告)日：1998-08-04
申请号：US529772
申请日：1995-09-18
CPC分类号： G06F17/5045 , H01L2924/0002
摘要： A process and implementing computer system (13) for updating circuit representations in a hierarchical Directed Acyclic Graph (DAG) format (400-410) based upon changes made to the primitive components of the circuit in a flat representation (201-213) includes performing a depth first search (505) on the hierarchical representation of the circuit beginning at the root level (501) for a given path. At each lower level, each child instance is visited (505) and if there is any change in any attribute between the hierarchical and flat representations (509), the component in the hierarchical representation which needs to be changed is copied (807) and connected to the children components of the original hierarchical representation. Changes in the attributes of the children components are made in the copied component (809). If the new component already exists in the hierarchy 811, then that component is deleted (817), otherwise the copied component is returned (813), and changes are passed upwardly to the root level (815) where the previous DAG may be replaced with the copied and updated DAG which includes changes in the attributes of components of a corresponding flat circuit representation.
摘要翻译： 基于在平面表示（201-213）中对电路的原始分量进行的改变，用于以分级定向非循环图（DAG）格式（400-410）更新电路表示的处理和实现计算机系统（13）包括执行 关于从给定路径的根级（501）开始的电路的分层表示的深度第一搜索（505）。 在每个较低级别，每个子实例被访问（505），并且如果分层和平面表示（509）之间的任何属性有任何改变，则需要改变的分层表示中的组件被复制（807）并被连接 对原始分层表示的子组件。 在复制的组件（809）中进行子组件属性的更改。 如果新组件已经存在于层次结构811中，那么该组件被删除（817），否则返回复制的组件（813），并将更改向上传递到根级别（815），其中先前的DAG可以被替换为 复制和更新的DAG，其包括对应平面电路表示的组件的属性的改变。
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公开(公告)号：US07839129B2
公开(公告)日：2010-11-23
申请号：US12000090
申请日：2007-12-07
申请人： Sanjay Pant , David Theodore Blaauw
发明人： Sanjay Pant , David Theodore Blaauw
IPC分类号： G05F1/00
CPC分类号： H03K19/00361 , Y10T307/696 , Y10T307/729
摘要： An integrated circuit (100) is provided with power regulating circuitry (104) serving to actively regulate the voltage difference between a first power supply rail Vdd and a second power rail Vss being used to supply electrical power to processing circuitry (102). A voltage regulating capacitor Ca has one terminal connected to the first power rail Vdd and a second terminal selectively connected to either the second power rail Vss or a third power rail Vdda. Should a voltage undershoot be detected by voltage sensing circuitry 106, then the capacitor Ca is connected to the third power rail Vdda so as to dump at least part of charge Ca, Vdda in capacitor Ca onto the first power rail Vdd and resist the voltage drop. During normal operation, charge is accumulated into the capacitor Ca. An additional load device T2 is provided to lower the voltage difference should an overshoot be detected.
摘要翻译： 集成电路（100）设置有功率调节电路（104），用于主动地调节用于向处理电路（102）提供电力的第一电源轨Vdd和第二电源轨Vss之间的电压差。 电压调节电容器Ca具有连接到第一电源轨Vdd的一个端子和选择性地连接到第二电力轨Vss或第三电力轨Vdda的第二端子。 如果由电压感测电路106检测到电压下冲，则电容器Ca连接到第三电力轨Vdda，以将电容器Ca中的电荷Ca，Vdda的至少一部分转储到第一电源轨Vdd上并抵抗电压降 。 在正常操作期间，电荷积累到电容器Ca中。 提供额外的负载装置T2以便在检测到过冲时降低电压差。
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公开(公告)号：US20100235697A1
公开(公告)日：2010-09-16
申请号：US12382427
申请日：2009-03-16
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177
摘要： An integrated circuit 2 is provided with domino logic including a speculative node 22 and a checker node 24. Precharged circuitry 36 precharges both the speculative node and the checker node. Logic circuitry 26 provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry 28, 30 first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry 26 have appropriate values. Error detection circuitry 32 detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译： 集成电路2具有包括推测节点22和检验器节点24的多米诺逻辑逻辑。预充电电路36对推测节点和检验器节点进行预充电。 逻辑电路26根据输入信号值提供推测节点和校验器节点的放电路径。 评估控制电路28,30首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路26的输入信号具有适当的值，则它们可以被放电。 错误检测电路32在推测节点和检查器节点都不是放电的两者之一或两者未被充电时检测错误。
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公开(公告)号：US20100220542A1
公开(公告)日：2010-09-02
申请号：US12379820
申请日：2009-03-02
IPC分类号： G11C8/00
CPC分类号： G11C11/419
摘要： A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.
摘要翻译： 集成电路存储器内的存储器单元36具有耦合到第一传输门38和第二传输门40的访问控制器32.在对存储单元38的写访问期间，第一传输门38和第二传输门 40打开。 在读取访问期间，打开第一传递门38并关闭第二传递门40。 读写操作中的这种不对称允许形成存储单元36的门的不对称性，从而允许改变增加读稳健性和写鲁棒性。 不同栅极的设计参数中的不对称可以采取改变栅极长度，栅极宽度和阈值电压的形式，以便改变不同栅极的电导以适应其在存储单元36内的各自的作用 由分离的字线提供的非对称方式驱动读操作和写操作。
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公开(公告)号：US20100217562A1
公开(公告)日：2010-08-26
申请号：US12379617
申请日：2009-02-25
申请人： David Theodore Blaauw , Dennis Michael Sylvester , David Alan Fick , Stuart David Biles , Michael John Wieckowski , Scott McLean Hanson , Gregory Kengho Chen
发明人： David Theodore Blaauw , Dennis Michael Sylvester , David Alan Fick , Stuart David Biles , Michael John Wieckowski , Scott McLean Hanson , Gregory Kengho Chen
CPC分类号： G05B21/02 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.
摘要翻译： 一种用于处理数据2的装置设置有时间 - 数字转换器18，其用于通过一个或多个通过处理级的信号路径来测量信号处理延迟。 该测量的延迟产生表示已经测量的信号处理延迟的多个实例的延迟值。 在软件控制下执行分析以基于已经产生的延迟值来估计通过处理阶段的最差情况信号处理延迟。 进行装置的工作参数（例如电源电压和时钟频率）的调整，以通过处理阶段提供足够的时间余量，以满足在没有过多余量的情况下估计的最差情况信号处理延迟。
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公开(公告)号：US07263015B2
公开(公告)日：2007-08-28
申请号：US11267574
申请日：2005-11-07
CPC分类号： G11C11/418 , G11C8/08 , G11C8/10
摘要： A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.
摘要翻译： 一种信号捕捉元件，用于在预充电周期期间提供第一预充电逻辑电平作为第一和第二中间地址部分信号，并且在评估周期期间输出地址部分逻辑电平作为第一中间地址部分信号和反相地址部分 逻辑电平作为第二临时地址部分信号。 第一和第二地址部分信号可以分别从第一和第二临时地址部分信号导出。 一种逆变器电路，用于在预充电周期期间将作为第一和第二地址部分信号的第二预充电逻辑电平输出到地址译码器。 逆变器电路具有保持电压电平的传输特性，使得第一和第二地址部分信号被解释为处于第二预充电逻辑电平，尽管第一或第二临时地址部分信号在期间不能转换到有效逻辑电平 评估期
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公开(公告)号：US09335972B2
公开(公告)日：2016-05-10
申请号：US14093040
申请日：2013-11-29
申请人： Kaiyuan Yang , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick , Michael B. Henry , Yoonmyung Lee
发明人： Kaiyuan Yang , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick , Michael B. Henry , Yoonmyung Lee
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.
摘要翻译： 真正的随机数发生器包括环形振荡器，其在振荡开始时刻被触发以在第一振荡模式下开始振荡。 第一种振荡模式最终会依赖于热噪声而崩溃到第二种振荡模式。 测量从振荡开始时间到振荡器塌陷到第二模式的时间的崩溃时间，并且这可以用于确定随机数。 TRNG可以使用标准数字技术完全合成，能够提供高随机性，良好的吞吐量和能量效率。
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公开(公告)号：US09036405B1
公开(公告)日：2015-05-19
申请号：US14092395
申请日：2013-11-27
IPC分类号： G11C11/419 , G11C7/06
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C7/08 , G11C11/419
摘要： Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to control the sense amplifier circuitry to operate in a plurality of modes including an offset compensation mode, an amplification mode and a latching mode.
摘要翻译： 存储器电路包括一个6位元单元6的阵列，其中位单元的列通过连接到相应读出放大器电路10的位线对8耦合在一起。 读出放大器电路包括反相器对12,14和控制电路，其被配置为控制读出放大器电路以包括偏移补偿模式，放大模式和锁存模式的多种模式操作。
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