公开(公告)号：US5571737A

公开(公告)日：1996-11-05

申请号：US280113

申请日：1994-07-25

申请人： Shing-Ren Sheu ,  Chung-Yuan Lee

发明人： Shing-Ren Sheu ,  Chung-Yuan Lee

IPC分类号： H01L21/336 ,  H01L27/02 ,  H01L21/265

CPC分类号： H01L29/66568 ,  H01L27/0251 ,  H01L27/0266

摘要： An improved structure and process of fabricating a metal oxide field effect (MOSFET) which has a high resistance to electro-static discharge. The device has pre-gate heavily doped source and drain regions which overlap the gate electrode and the source and drain regions. This improved MOSFET device with overlapping pre-gate source and drain regions is incorporated into an electro-static discharge (ESD) circuit to form a memory device which has a high resistance to electro-static discharge (ESD).The MOSFET device with pre-gate heavily doped source and drain regions can be formed as follows. Spaced pre-gate source and drain regions of a second conductivity type are formed in the substrate with a background doping of a first conductivity type. A gate oxide and a gate is formed in the regions between the pre-gate source and drain regions. The gate at least partially overhangs the pre-gate source and drain regions. Subsequently, spacers are formed on the vertical sidewalls of the gate. Source and drain regions in the substrate are formed on either side of the spacers. Next, using conventional processes, insulating and metal layers are added to connect the circuit elements and form a memory device. The device is connected to form the input and input/output ESD circuits. The combination of the device of the invention and the ESD protection circuit forms an ESD resistant circuit using a minimum number of manufacturing steps.

摘要翻译： 改进了对静电放电具有高抗性的金属氧化物场效应（MOSFET）的制造结构和工艺。 该器件具有与栅电极和源极和漏极区重叠的预栅极重掺杂源极和漏极区。 这种具有重叠预栅极源极和漏极区域的改进的MOSFET器件被并入到静电放电（ESD）电路中，以形成具有高抗静电放电（ESD）的存储器件。 具有预栅极重掺杂源极和漏极区的MOSFET器件可以如下形成。 具有第二导电类型的间隔的预栅极源极和漏极区域形成在具有第一导电类型的背景掺杂的衬底中。 在栅极源极和漏极区域之间的区域中形成栅极氧化物和栅极。 栅极至少部分地悬垂在栅极之前的源极和漏极区域。 随后，在栅极的垂直侧壁上形成间隔物。 衬底中的源区和漏区形成在间隔物的两侧。 接下来，使用常规方法，添加绝缘和金属层以连接电路元件并形成存储器件。 该器件被连接以形成输入和输入/输出ESD电路。 本发明的器件与ESD保护电路的组合使用最少数量的制造步骤形成耐ESD电路。

公开(公告)号：US07592233B2

公开(公告)日：2009-09-22

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。

公开(公告)号：US07446355B2

公开(公告)日：2008-11-04

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US20080067569A1

公开(公告)日：2008-03-20

申请号：US11751572

申请日：2007-05-21

申请人： Sheng-Tsung Chen ,  Shiah-Jyh Lin ,  Chung-Yuan Lee

发明人： Sheng-Tsung Chen ,  Shiah-Jyh Lin ,  Chung-Yuan Lee

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

摘要： A method for fabricating a vertical transistor. At least one deep trench is formed in a silicon substrate. A conductive structure and a trench top insulator are successively formed in the deep trench, in which the conductive structure comprises a first doping region and the trench top insulator is below the surface of the silicon substrate. An epitaxial silicon layer is formed on the surface of the silicon substrate. Ion implantation is performed in the epitaxial silicon layer to form a second doping region therein. A gate structure is formed on the trench top insulator, protruding from the surface of the epitaxial silicon layer and adjacent to the sidewalls of the epitaxial silicon layer and the deep trench. A capping layer is formed on the epitaxial silicon layer. The invention also discloses a memory device with a vertical transistor and a method for fabricating the same.

摘要翻译： 一种垂直晶体管的制造方法。 在硅衬底中形成至少一个深沟槽。 在深沟槽中连续地形成导电结构和沟槽顶部绝缘体，其中导电结构包括第一掺杂区域，并且沟槽顶部绝缘体位于硅衬底的表面下方。 在硅衬底的表面上形成外延硅层。 在外延硅层中进行离子注入，以在其中形成第二掺杂区。 栅极结构形成在沟槽顶部绝缘体上，从外延硅层的表面突出并且邻近外延硅层和深沟槽的侧壁。 在外延硅层上形成覆盖层。 本发明还公开了一种具有垂直晶体管的存储器件及其制造方法。

公开(公告)号：US20050221560A1

公开(公告)日：2005-10-06

申请号：US11139450

申请日：2005-05-27

申请人： Yu-Sheng Shu ,  Yuan-Hsun Wu ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Yu-Sheng Shu ,  Yuan-Hsun Wu ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  H01L21/027 ,  H01L21/308 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/02

CPC分类号： H01L27/1087 ,  H01L21/3083 ,  H01L27/0207 ,  H01L27/10864

摘要： A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.

摘要翻译： 一种形成具有矩形沟槽的垂直存储器件的方法。 首先，提供由光致抗蚀剂层覆盖的基板。 接下来，通过掩模限定光致抗蚀剂层以形成矩形开口，其中掩模具有以预定间隔布置的两个矩形透明图案。 接下来，使用限定的光致抗蚀剂层作为掩模来蚀刻基板以形成单个矩形沟槽，然后除去光致抗蚀剂层。 最后，在矩形沟槽中依次形成沟槽电容器和垂直晶体管，以完成垂直存储器件。

公开(公告)号：US20050020028A1

公开(公告)日：2005-01-27

申请号：US10690859

申请日：2003-10-22

申请人： Chien-Mao Liao ,  Tzu-En Ho ,  Chang-Rong Wu ,  Chih-How Chang ,  Sheng-Wei Yang ,  Sheng-Tsung Chen ,  Chung-Yuan Lee ,  Wen-Sheng Liao ,  Chen-Chou Huang

发明人： Chien-Mao Liao ,  Tzu-En Ho ,  Chang-Rong Wu ,  Chih-How Chang ,  Sheng-Wei Yang ,  Sheng-Tsung Chen ,  Chung-Yuan Lee ,  Wen-Sheng Liao ,  Chen-Chou Huang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229

摘要： A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

摘要翻译： 一种形成沟槽隔离的方法。 提供具有开口的半导体衬底，其上形成有掩模层。 在半导体衬底和沟槽上顺应地形成第一绝缘层，并且沟槽被第一绝缘层填充。 将第一绝缘层各向异性地蚀刻到半导体衬底的下面。 在半导体衬底和沟槽上形成第二绝缘层。 将第二绝缘层平坦化以露出掩模层。

公开(公告)号：US5698458A

公开(公告)日：1997-12-16

申请号：US680101

申请日：1996-07-15

申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Chung-Yuan Lee ,  Ming-Tzong Yang

发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Chung-Yuan Lee ,  Ming-Tzong Yang

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823892

摘要： A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.

摘要翻译： 一种制造半导体器件的方法包括在所述器件的表面上形成二氧化硅膜，在所述二氧化硅膜的表面上形成氮化硅图案，将离子注入所述衬底中，与所述氮化硅中的至少一些相邻 第一极性的阱区的图案，在所述器件上形成掩模，并且将具有相反极性的离子深入离子注入到相反极性的阱区中。

公开(公告)号：US5576557A

公开(公告)日：1996-11-19

申请号：US422225

申请日：1995-04-14

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0259 ,  H01L27/0251

摘要： An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

摘要翻译： 公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。 一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。 第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。 第二SCR的阴极和阴极栅极连接到第二电源端子。 第二SCR的阳极连接到其相关的I / O缓冲垫。 第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

公开(公告)号：US5289334A

公开(公告)日：1994-02-22

申请号：US978332

申请日：1992-11-18

申请人： Ming-Dou Ker ,  Chung-Yuan Lee ,  Chung-Yu Wu

发明人： Ming-Dou Ker ,  Chung-Yuan Lee ,  Chung-Yu Wu

IPC分类号： H01L27/02 ,  H02H9/04 ,  H02H9/00 ,  H02H3/22

CPC分类号： H01L27/0262 ,  H01L27/0251 ,  H01L27/0259 ,  H02H9/046

摘要： A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply terminals, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated components are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

摘要翻译： 用于保护CMOS芯片免受静电放电（ESD）损坏的电路在被保护线路和两个电源端子VDD和VSS之间连接有四个SCR。 将SCR极化以对每个电源端子进行任一极性的ESD电流。 用于SCR和相关部件的双极晶体管以有利的方式布置在芯片中，这降低了输入/输出寄生电容并且提高了具有低ESD触发电压的所提出的电路的保护能力。

公开(公告)号：US08193648B2

公开(公告)日：2012-06-05

申请号：US12758289

申请日：2010-04-12

申请人： Yuan Ku Lan ,  Chung-Yuan Lee

发明人： Yuan Ku Lan ,  Chung-Yuan Lee

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： G03F7/70633 ,  G03F9/7076

摘要： An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.

摘要翻译： 公开了用于检测预层和当前层之间的光刻工艺的暴露误差的集成对准和覆盖标记。 集成对齐和重叠标记包括在相同拍摄区域中的对准标记和重叠标记。 对准标记形成在覆盖标记周围; 因此，为了检查光刻工艺的对准精度，可以计算预层和当前层之间的间隙或取向。