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公开(公告)号：US20240057487A1
公开(公告)日：2024-02-15
申请号：US17938926
申请日：2022-09-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kai-Jiun Chang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H01L45/1233 , H01L45/146 , H01L45/1675 , H01L27/2472 , G11C13/0007
Abstract: An RRAM includes a bottom electrode, a resistive switching layer and a top electrode. The bottom electrode includes an inverted T-shaped profile. The resistive switching layer covers the bottom electrode. The top electrode covers the resistive switching layer. The inverted T-shaped profile includes a bottom element and a vertical element. The vertical element is disposed on the bottom element. The shape of the vertical element includes a rectangle or a trapezoid.
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公开(公告)号：US11632888B2
公开(公告)日：2023-04-18
申请号：US17571519
申请日：2022-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
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公开(公告)号：US20220359618A1
公开(公告)日：2022-11-10
申请号：US17870814
申请日：2022-07-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.
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公开(公告)号：US11489114B2
公开(公告)日：2022-11-01
申请号：US17211875
申请日：2021-03-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shu-Hung Yu , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L45/00
Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.
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公开(公告)号：US20220209112A1
公开(公告)日：2022-06-30
申请号：US17159160
申请日：2021-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.
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Patent Agency Ranking
公开(公告)号：US11257864B2
公开(公告)日：2022-02-22
申请号：US16794194
申请日：2020-02-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
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公开(公告)号：US11094880B2
公开(公告)日：2021-08-17
申请号：US16504491
申请日：2019-07-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.
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公开(公告)号：US10608006B2
公开(公告)日：2020-03-31
申请号：US16038197
申请日：2018-07-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L27/115 , H01L27/11568 , H01L29/792 , H01L21/28
Abstract: A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.
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公开(公告)号：US20200013793A1
公开(公告)日：2020-01-09
申请号：US16038197
申请日：2018-07-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L27/11568 , H01L21/28 , H01L29/792
Abstract: A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.
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公开(公告)号：US10340282B1
公开(公告)日：2019-07-02
申请号：US15895886
申请日：2018-02-13
Applicant: United Microelectronics Corp.
Inventor： Shu-Hung Yu , Chun-Hung Cheng , Chuan-Fu Wang , An-Hsiu Cheng , Ping-Chia Shih , Chi-Cheng Huang , Kuo-Lung Li , Chia-Hui Huang , Chih-Yao Wang , Zi-Jun Liu , Chih-Hao Pan
IPC: H01L21/18 , H01L27/1157 , H01L21/762 , H01L23/528 , H01L29/06
Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.
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