公开(公告)号：US11944016B2

公开(公告)日：2024-03-26

申请号：US17692203

申请日：2022-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.

公开(公告)号：US11335729B2

公开(公告)日：2022-05-17

申请号：US17074643

申请日：2020-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Hung-Chan Lin ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: G11C11/16 ,  H01L27/22 ,  H01L23/48 ,  H01L43/12 ,  H01L23/544 ,  H01L21/321 ,  H01L21/762 ,  H01L23/485

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

公开(公告)号：US10797226B2

公开(公告)日：2020-10-06

申请号：US16148852

申请日：2018-10-01

Applicant: United Microelectronics Corp.

Inventor： Ya-Sheng Feng ,  Yu-Chun Chen ,  Chiu-Jung Chiu ,  Hung-Chan Lin

IPC: H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01F10/32 ,  H01L27/22 ,  H01F41/34 ,  G11C11/16 ,  H01L43/12

Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.

公开(公告)号：US10593865B2

公开(公告)日：2020-03-17

申请号：US15904429

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

公开(公告)号：US20190237660A1

公开(公告)日：2019-08-01

申请号：US15904429

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

公开(公告)号：US20180151666A1

公开(公告)日：2018-05-31

申请号：US15362771

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tri-Rung Yew ,  Hung-Chan Lin ,  Li-Wei Feng ,  Chien-Ting Ho ,  Chia-Lung Chang

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L27/108

CPC classification number: H01L28/82 ,  H01L21/31111 ,  H01L21/32051 ,  H01L27/10852

Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.

公开(公告)号：US20180130871A1

公开(公告)日：2018-05-10

申请号：US15346717

申请日：2016-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L49/02

CPC classification number: H01L28/88

Abstract: The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.

公开(公告)号：US12256556B2

公开(公告)日：2025-03-18

申请号：US18595376

申请日：2024-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

公开(公告)号：US20250078891A1

公开(公告)日：2025-03-06

申请号：US18950204

申请日：2024-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

公开(公告)号：US20240389473A1

公开(公告)日：2024-11-21

申请号：US18788163

申请日：2024-07-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A semiconductor device includes a spin orbit torque (SOT) layer on a substrate, a magnetic tunneling junction (MTJ) on the SOT layer, a hard mask on the MTJ, and a cap layer on and directly contacting the SOT layer and the hard mask. Preferably, the cap layer directly on the SOT layer and the cap layer on sidewalls of the MTJ have different thicknesses and a sidewall of the cap layer is aligned with a sidewall of the SOT layer.