公开(公告)号：US20180166441A1

公开(公告)日：2018-06-14

申请号：US15825057

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US09748349B2

公开(公告)日：2017-08-29

申请号：US14723467

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Wei-Hao Huang

IPC: H01L29/423 ,  H01L21/768 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/42364 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/51 ,  H01L29/518 ,  H01L29/785

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

公开(公告)号：US09685531B2

公开(公告)日：2017-06-20

申请号：US15263349

申请日：2016-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66628

Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.

公开(公告)号：US20170125291A1

公开(公告)日：2017-05-04

申请号：US15404163

申请日：2017-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

公开(公告)号：US20170077031A1

公开(公告)日：2017-03-16

申请号：US14882424

申请日：2015-10-13

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L23/535 ,  H01L29/06 ,  H01L29/165 ,  H01L21/265 ,  H01L29/24 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

Abstract translation: 半导体器件及其制造方法，半导体器件包括鳍状结构，栅极结构，外延层，锗层，层间介电层和第一插塞。 鳍状结构设置在基板上。 栅极结构跨过鳍状结构形成。 外延层设置在与栅极结构相邻的鳍状结构中。 锗层设置在外延层上。 层间绝缘层覆盖基板和翅片形结构。 第一插头设置在层间电介质层中以与锗层接触。

公开(公告)号：US20160172300A1

公开(公告)日：2016-06-16

申请号：US14591936

申请日：2015-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构上形成牺牲层; 在牺牲层和ILD层中形成第一接触塞; 去除牺牲层; 以及在所述栅极结构和所述第一接触插塞上形成第一电介质层。

公开(公告)号：US09337084B1

公开(公告)日：2016-05-10

申请号：US14846822

申请日：2015-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Kun-Yuan Liao ,  Chun-Lung Chen ,  Ching-Pin Hsu ,  Shang-Yuan Tsai

IPC: H01L21/768 ,  H01L27/11

CPC classification number: H01L21/76816 ,  H01L21/76801 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.

Abstract translation: 本发明提供了一种用于制造半导体器件的接触孔的方法，包括第一介电层，第一介电层和第二区分别形成在第一介电层上，形成至少两个切割硬掩模， 第一区域和第二区域分别设置在切割硬掩模正下方的至少两个台阶部分。 之后，形成在第一区域内的至少一个第一狭槽开口，其中第一狭槽开口部分地与切割硬掩模重叠并且直接接触切割硬掩模，并且在第二区域内形成至少一个第二接触开口， 第二接触开口不直接接触切割硬掩模，并且形成至少两个接触孔，其中每个接触孔穿过每个台阶高度部分。

公开(公告)号：US20160071944A1

公开(公告)日：2016-03-10

申请号：US14510126

申请日：2014-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66628

Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.

Abstract translation: 具有金属栅极的半导体器件包括衬底，位于衬底上的第一金属栅极和位于衬底上的第二金属栅极。 第一金属栅极包括第一功函数金属层，第一功函数金属层包括锥形顶部。 第二金属栅极包括第二功函数金属层。 第一功函数金属层和第二功函数金属层彼此互补。

公开(公告)号：US20160020144A1

公开(公告)日：2016-01-21

申请号：US14332375

申请日：2014-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/532 ,  H01L21/311 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a device thereon; forming a dielectric layer on the device and the substrate; forming a first mask layer on the dielectric layer; removing part of the first mask layer and part of the dielectric layer for forming a patterned first mask layer on the dielectric layer; covering a hard mask on the patterned first mask layer and the dielectric layer; partially removing the hard mask for forming a spacer adjacent to the patterned first mask layer and the dielectric layer; forming a contact hole adjacent to the spacer; filling the contact hole with a metal layer; and planarizing the metal layer for forming a contact plug, wherein the contact plug contacts the dielectric layer and the spacer simultaneously.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个装置的基板; 在所述器件和所述衬底上形成介电层; 在所述电介质层上形成第一掩模层; 去除所述第一掩模层的一部分和所述电介质层的一部分，以在所述电介质层上形成图案化的第一掩模层; 覆盖图案化的第一掩模层和电介质层上的硬掩模; 部分去除用于形成邻近图案化的第一掩模层和电介质层的隔离物的硬掩模; 形成与间隔件相邻的接触孔; 用金属层填充接触孔; 以及平坦化用于形成接触插塞的金属层，其中所述接触插塞同时接触所述电介质层和所述间隔物。

公开(公告)号：US12261052B2

公开(公告)日：2025-03-25

申请号：US18608940

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H10D30/01 ,  H01L21/306 ,  H01L21/308 ,  H10D30/47 ,  H10D62/824 ,  H10D62/85

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.