公开(公告)号：US11251279B2

公开(公告)日：2022-02-15

申请号：US16936442

申请日：2020-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.

公开(公告)号：US20210050441A1

公开(公告)日：2021-02-18

申请号：US17087646

申请日：2020-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

公开(公告)号：US10756209B2

公开(公告)日：2020-08-25

申请号：US16812358

申请日：2020-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.

公开(公告)号：US10103265B1

公开(公告)日：2018-10-16

申请号：US15696187

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Yi-Che Yen

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

Abstract: A CMOS device is disclosed, including a plurality of active regions having a length along a first direction, wherein the active regions are arranged end-to-end along the first direction and are separated by an isolation structure. A recessed region is formed in the isolation structure between the adjacent terminals of the each pair of neighboring active regions and is completely filled by an interlayer dielectric layer, wherein the interlayer dielectric layer comprises a stress.

公开(公告)号：US20180012992A1

公开(公告)日：2018-01-11

申请号：US15238696

申请日：2016-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Yu-Hao Huang ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.

公开(公告)号：US20240413199A1

公开(公告)日：2024-12-12

申请号：US18811821

申请日：2024-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

公开(公告)号：US12107157B2

公开(公告)日：2024-10-01

申请号：US18223543

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/20 ,  H01L21/308 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US20240047554A1

公开(公告)日：2024-02-08

申请号：US17899604

申请日：2022-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Huai-Tzu Chiang ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/31

CPC classification number: H01L29/66462 ,  H01L29/778 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.

公开(公告)号：US20240021702A1

公开(公告)日：2024-01-18

申请号：US17885574

申请日：2022-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Huai-Tzu Chiang ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786

Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.

公开(公告)号：US20230361207A1

公开(公告)日：2023-11-09

申请号：US18223543

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.