公开(公告)号：US06366128B1

公开(公告)日：2002-04-02

申请号：US09655168

申请日：2000-09-05

申请人： Atul V. Ghia ,  Suresh M. Menon ,  David P. Schultz

发明人： Atul V. Ghia ,  Suresh M. Menon ,  David P. Schultz

IPC分类号： H03K19094

CPC分类号： H04L25/0272 ,  H03K5/151 ,  H03K19/018528 ,  H04L25/028

摘要： Described are systems for producing differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

摘要翻译： 描述了用于产生差分逻辑信号的系统。 这些系统可以通过编程一个或多个可编程元件而适用于不同的负载。 一个实施例包括一系列驱动级，其输出彼此连接。 驱动器阶段依次打开，提供越来越强大的差分放大。 放大的逐渐增加产生输出电阻的相应逐渐降低，这降低了与信号反射相关联的噪声。 这些系统可以并入可编程IOB中，以使PLD能够提供差分输出信号。

公开(公告)号：US06262596B1

公开(公告)日：2001-07-17

申请号：US09374471

申请日：1999-08-13

申请人： David P. Schultz ,  Lawrence C. Hung ,  F. Erich Goetting

发明人： David P. Schultz ,  Lawrence C. Hung ,  F. Erich Goetting

IPC分类号： H03K19177

CPC分类号： H03M13/09

摘要： A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

摘要翻译： 一种用于可编程逻辑器件（PLD）的总线接口电路，包括连接在两个或多个外部通信电路和配置存储器阵列之间的接口多路复用器。 接口多路复用器协调所选择的一个外部通信电路和分组处理器之间的通信。 分组处理器解译从所选择的外部通信电路在比特流中发送的命令/数据信息。 在默认状态下，接口多路复用器将PLD的双用途输入/输出引脚连接到数据包处理器。 在替代状态下，接口多路复用器将JTAG接口电路连接到分组处理器，以便于通过PLD的JTAG引脚进行配置操作。

公开(公告)号：US6005423A

公开(公告)日：1999-12-21

申请号：US546345

申请日：1995-10-20

申请人： David P. Schultz

发明人： David P. Schultz

IPC分类号： H03K17/22

CPC分类号： H03K17/223

摘要： A power-on reset circuit responds to a power decrease of very short duration by using a delay circuit having a high threshold inverter which reliably detects a voltage as high as a standard threshold voltage as a low voltage when the power supply voltage again begins to increase. A very low current source provides current for driving the power-on reset circuit only when providing a power-on reset signal and draws no current during normal circuit operation.

摘要翻译： 上电复位电路通过使用具有高阈值逆变器的延迟电路来响应非常短的持续时间的功率降低，当电源电压再次开始增加时，可靠地检测到作为标准阈值电压的电压为低电压为低电压 。 非常低的电流源仅在提供上电复位信号时提供用于驱动上电复位电路的电流，并且在正常电路操作期间不消耗电流。

公开(公告)号：US07165950B2

公开(公告)日：2007-01-23

申请号：US10736161

申请日：2003-12-15

申请人： Carlos A. Fenny ,  Darrel B. Bryan ,  David P. Schultz

发明人： Carlos A. Fenny ,  Darrel B. Bryan ,  David P. Schultz

IPC分类号： F04B1/26 ,  F04B49/24 ,  F15B21/02 ,  F16D31/02 ,  F04F1/00

CPC分类号： F15B13/024 ,  F04B1/2042 ,  F04B3/006 ,  F15B20/007 ,  F15B2211/20546 ,  F15B2211/50518 ,  F15B2211/511 ,  F15B2211/5157 ,  F15B2211/528 ,  F15B2211/8752 ,  Y10T137/2761

摘要： A two-stage pressure relief valve for use with hydraulic systems is disclosed. The two-stage pressure relief valve has a first stage that relieves increases in hydraulic system pressure over the normal operating pressure and up to a selected threshold pressure level, and a second stage that brings the hydraulic system pressure down to a selected reduced operating pressure that is below the normal operating pressure in response to increases in the operating pressure over the threshold pressure level.

摘要翻译： 公开了一种用于液压系统的两级减压阀。 两级减压阀具有第一级，其减轻液压系统压力在正常工作压力和高达所选阀值压力水平之上的增加，以及将液压系统压力降低至所选择的降低的操作压力的第二级， 响应于超过阈值压力水平的操作压力的增加而低于正常工作压力。

公开(公告)号：US07111217B1

公开(公告)日：2006-09-19

申请号：US10086129

申请日：2002-02-28

申请人： David P. Schultz

发明人： David P. Schultz

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318555

摘要： A flexible architecture for nesting joint test action group (JTAG) test access port (TAP) controllers for FPGA-based embedded system-on-chip (SoC) is provided. Advantageously, a programmable approach permits bits in a selectable bit register (302) to be selected based on the number of JTAG TAPs that will be utilized. The selected bits can be used to vary the apparent length of an instruction register (302). Importantly, the flexible architecture permits access to any combination of a plurality of JTAG TAP controllers in the FPGA-based embedded SoC without the need to rewire any I/O pins of the FPGA and/or embedded IP cores.

摘要翻译： 提供了一种用于嵌套基于嵌入式系统级芯片（SoC）的联合测试动作组（JTAG）测试访问端口（TAP）控制器的灵活架构。 有利地，可编程方法允许基于将被使用的JTAG TAP的数量来选择可选位寄存器（302）中的位。 所选位可用于改变指令寄存器（302）的视在长度。 重要的是，灵活的架构允许访问基于FPGA的嵌入式SoC中的多个JTAG TAP控制器的任何组合，而不需要重新连接FPGA和/或嵌入式IP内核的任何I / O引脚。

公开(公告)号：US07109746B1

公开(公告)日：2006-09-19

申请号：US10806697

申请日：2004-03-22

申请人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

发明人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/1776

摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

摘要翻译： 描述用于错误检测的数据监视的方法和装置。 可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。 功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。 主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。 辅助地址线耦合到与功能发生器相关联的存储器单元组。 掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

公开(公告)号：US06489837B2

公开(公告)日：2002-12-03

申请号：US10007167

申请日：2001-11-30

申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

IPC分类号： G05F110

CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

摘要翻译： 提供一种用于控制集成电路芯片上的电路的阻抗的系统。 选择至少一个电路作为p沟道参考电路工作，并且选择至少一个电路作为n沟道参考电路进行工作。 选择其他电路用作电路和/或线路终端电路。 数字控制阻抗（DCI）电路控制p沟道参考电路以确定用于电路中的p沟道晶体管的期望配置。 DCI电路进一步控制n沟道参考电路以确定在电路中使用的n沟道晶体管的期望配置。 DCI电路考虑了p沟道参考电路中p沟道晶体管的电阻，n沟道参考电路中n沟道晶体管的电阻以及温度，电压和工艺变化等因素。 DCI电路将识别n沟道和p沟道晶体管的期望配置的信息中继到电路。 然后响应于该信息配置电路。

公开(公告)号：US06445245B1

公开(公告)日：2002-09-03

申请号：US09684539

申请日：2000-10-06

申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

IPC分类号： G05F110

CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

公开(公告)号：US06353334B1

公开(公告)日：2002-03-05

申请号：US09492560

申请日：2000-01-27

申请人： David P. Schultz ,  Brian Von Herzen ,  Jon A. Brunetti

发明人： David P. Schultz ,  Brian Von Herzen ,  Jon A. Brunetti

IPC分类号： H03K190185

CPC分类号： H03K19/017545

摘要： Described are a system and method for converting a typical two-level logic signal to a pair of differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output terminals. A resistor network connected to these output terminals converts the complementary signals to a pair of differential signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.

摘要翻译： 描述了将典型的两级逻辑信号转换成一对差分逻辑信号的系统和方法。 根据一个实施例，现场可编程门阵列（FPGA）被配置为在一对输出端子上提供数字信号及其补码。 连接到这些输出端子的电阻网络将互补信号转换成具有由LVDS规范建立的范围内的电流和电压电平的一对差分信号。 为了获得最大的效率，可以选择构成电阻网络的电阻值与LVDS接收机所表现的100欧姆输入电阻相匹配。

公开(公告)号：US09156547B2

公开(公告)日：2015-10-13

申请号：US13370130

申请日：2012-02-09

申请人： Corey J. Dickman ,  Carlos A. Fenny ,  David P. Schultz

发明人： Corey J. Dickman ,  Carlos A. Fenny ,  David P. Schultz

IPC分类号： F01D7/00 ,  B64C27/605 ,  F15B18/00

CPC分类号： B64C27/605 ,  F15B18/00

摘要： The main rotor control system includes a rise/fall swashplate assembly that is coupled to three triplex actuators. The swashplate assembly is configured to provide full collective and cyclic pitch controls. Each triplex actuator includes three piston/cylinder assemblies in parallel. Selective actuation of each triplex actuator is controlled by a fly-by-wire system in conjunction with three flight control computers and three hydraulic power packs. Integrated three function valves can be associated with an individual manifold for each piston/cylinder assembly of each triplex actuator, the integrated three function valve be configured to insure safe operation of the triplex actuator during a failure of a certain piston/cylinder assembly.

摘要翻译： 主转子控制系统包括一个上升/下降斜盘组件，它与三个三重执行器相连。 斜盘组件被配置为提供完整的集体和循环俯仰控制。 每个三重执行器都包括并联的三个活塞/气缸组件。 每个三重执行机构的选择性致动由三线式控制计算机和三台液压动力组件联合控制。 集成的三功能阀可以与每个三重执行器的每个活塞/气缸组件的单独歧管相关联，集成的三功能阀被配置为在某个活塞/气缸组件的故障期间确保三重致动器的安全操作。